mirror of
https://github.com/PabloMK7/citra.git
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Merge pull request #31 from neobrain/gpu_framebuffer
GPU framebuffer emulation improvements
This commit is contained in:
bunnei
commit
daa924b906
11 changed files with 595 additions and 238 deletions
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@ -28,22 +28,24 @@ QVariant GPUCommandStreamItemModel::data(const QModelIndex& index, int role) con
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const GSP_GPU::GXCommand& command = GetDebugger()->ReadGXCommandHistory(command_index);
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if (role == Qt::DisplayRole)
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{
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std::map<GSP_GPU::GXCommandId, const char*> command_names;
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command_names[GSP_GPU::GXCommandId::REQUEST_DMA] = "REQUEST_DMA";
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command_names[GSP_GPU::GXCommandId::SET_COMMAND_LIST_FIRST] = "SET_COMMAND_LIST_FIRST";
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command_names[GSP_GPU::GXCommandId::SET_MEMORY_FILL] = "SET_MEMORY_FILL";
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command_names[GSP_GPU::GXCommandId::SET_DISPLAY_TRANSFER] = "SET_DISPLAY_TRANSFER";
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command_names[GSP_GPU::GXCommandId::SET_TEXTURE_COPY] = "SET_TEXTURE_COPY";
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command_names[GSP_GPU::GXCommandId::SET_COMMAND_LIST_LAST] = "SET_COMMAND_LIST_LAST";
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QString str = QString("%1 %2 %3 %4 %5 %6 %7 %8 %9").arg(command_names[static_cast<GSP_GPU::GXCommandId>(command.id)])
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.arg(command.data[0], 8, 16, QLatin1Char('0'))
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.arg(command.data[1], 8, 16, QLatin1Char('0'))
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.arg(command.data[2], 8, 16, QLatin1Char('0'))
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.arg(command.data[3], 8, 16, QLatin1Char('0'))
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.arg(command.data[4], 8, 16, QLatin1Char('0'))
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.arg(command.data[5], 8, 16, QLatin1Char('0'))
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.arg(command.data[6], 8, 16, QLatin1Char('0'))
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.arg(command.data[7], 8, 16, QLatin1Char('0'));
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std::map<GSP_GPU::GXCommandId, const char*> command_names = {
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{ GSP_GPU::GXCommandId::REQUEST_DMA, "REQUEST_DMA" },
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{ GSP_GPU::GXCommandId::SET_COMMAND_LIST_FIRST, "SET_COMMAND_LIST_FIRST" },
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{ GSP_GPU::GXCommandId::SET_MEMORY_FILL, "SET_MEMORY_FILL" },
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{ GSP_GPU::GXCommandId::SET_DISPLAY_TRANSFER, "SET_DISPLAY_TRANSFER" },
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{ GSP_GPU::GXCommandId::SET_TEXTURE_COPY, "SET_TEXTURE_COPY" },
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{ GSP_GPU::GXCommandId::SET_COMMAND_LIST_LAST, "SET_COMMAND_LIST_LAST" }
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};
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const u32* command_data = reinterpret_cast<const u32*>(&command);
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QString str = QString("%1 %2 %3 %4 %5 %6 %7 %8 %9").arg(command_names[command.id])
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.arg(command_data[0], 8, 16, QLatin1Char('0'))
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.arg(command_data[1], 8, 16, QLatin1Char('0'))
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.arg(command_data[2], 8, 16, QLatin1Char('0'))
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.arg(command_data[3], 8, 16, QLatin1Char('0'))
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.arg(command_data[4], 8, 16, QLatin1Char('0'))
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.arg(command_data[5], 8, 16, QLatin1Char('0'))
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.arg(command_data[6], 8, 16, QLatin1Char('0'))
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.arg(command_data[7], 8, 16, QLatin1Char('0'));
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return QVariant(str);
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}
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else
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@ -34,7 +34,7 @@
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/*
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* Standardized way to define a group of registers and corresponding data structures. To define
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* a new register set, first define struct containing an enumeration called "Id" containing
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* all register IDs and a template union called "Struct". Specialize the Struct union for any
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* all register IDs and a template struct called "Struct". Specialize the Struct struct for any
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* register ID which needs to be accessed in a specialized way. You can then declare the object
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* containing all register values using the RegisterSet<BaseType, DefiningStruct> type, where
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* BaseType is the underlying type of each register (e.g. u32).
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@ -54,7 +54,7 @@
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*
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* // declare register definition structures
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* template<Id id>
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* union Struct;
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* struct Struct;
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* };
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*
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* // Define register set object
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@ -62,10 +62,12 @@
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*
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* // define register definition structures
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* template<>
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* union Regs::Struct<Regs::Value1> {
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* struct Regs::Struct<Regs::Value1> {
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* union {
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* BitField<0, 4, u32> some_field;
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* BitField<4, 3, u32> some_other_field;
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* };
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* };
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*
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* Usage in external code (within SomeNamespace scope):
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*
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@ -77,7 +79,7 @@
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*
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*
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* @tparam BaseType Base type used for storing individual registers, e.g. u32
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* @tparam RegDefinition Class defining an enumeration called "Id" and a template<Id id> union, as described above.
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* @tparam RegDefinition Class defining an enumeration called "Id" and a template<Id id> struct, as described above.
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* @note RegDefinition::Id needs to have an enum value called NumIds defining the number of registers to be allocated.
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*/
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template<typename BaseType, typename RegDefinition>
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@ -16,6 +16,6 @@
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namespace ConfigMem {
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template <typename T>
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inline void Read(T &var, const u32 addr);
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void Read(T &var, const u32 addr);
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} // namespace
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@ -47,11 +47,6 @@ Handle g_shared_memory = 0;
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u32 g_thread_id = 0;
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enum {
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REG_FRAMEBUFFER_1 = 0x00400468,
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REG_FRAMEBUFFER_2 = 0x00400494,
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};
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/// Gets a pointer to the start (header) of a command buffer in GSP shared memory
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static inline u8* GX_GetCmdBufferPointer(u32 thread_id, u32 offset=0) {
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return Kernel::GetSharedMemoryPointer(g_shared_memory, 0x800 + (thread_id * 0x200) + offset);
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@ -67,38 +62,62 @@ void GX_FinishCommand(u32 thread_id) {
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// TODO: Increment header->index?
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}
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/// Read a GSP GPU hardware register
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void ReadHWRegs(Service::Interface* self) {
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static const u32 framebuffer_1[] = {GPU::PADDR_VRAM_TOP_LEFT_FRAME1, GPU::PADDR_VRAM_TOP_RIGHT_FRAME1};
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static const u32 framebuffer_2[] = {GPU::PADDR_VRAM_TOP_LEFT_FRAME2, GPU::PADDR_VRAM_TOP_RIGHT_FRAME2};
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/// Write a GSP GPU hardware register
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void WriteHWRegs(Service::Interface* self) {
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u32* cmd_buff = Service::GetCommandBuffer();
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u32 reg_addr = cmd_buff[1];
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u32 size = cmd_buff[2];
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u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]);
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switch (reg_addr) {
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// NOTE: Calling SetFramebufferLocation here is a hack... Not sure the correct way yet to set
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// whether the framebuffers should be in VRAM or GSP heap, but from what I understand, if the
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// user application is reading from either of these registers, then its going to be in VRAM.
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// Top framebuffer 1 addresses
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case REG_FRAMEBUFFER_1:
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GPU::SetFramebufferLocation(GPU::FRAMEBUFFER_LOCATION_VRAM);
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memcpy(dst, framebuffer_1, size);
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break;
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// Top framebuffer 2 addresses
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case REG_FRAMEBUFFER_2:
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GPU::SetFramebufferLocation(GPU::FRAMEBUFFER_LOCATION_VRAM);
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memcpy(dst, framebuffer_2, size);
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break;
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default:
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ERROR_LOG(GSP, "unknown register read at address %08X", reg_addr);
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// TODO: Return proper error codes
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if (reg_addr + size >= 0x420000) {
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ERROR_LOG(GPU, "Write address out of range! (address=0x%08x, size=0x%08x)", reg_addr, size);
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return;
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}
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// size should be word-aligned
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if ((size % 4) != 0) {
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ERROR_LOG(GPU, "Invalid size 0x%08x", size);
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return;
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}
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u32* src = (u32*)Memory::GetPointer(cmd_buff[0x4]);
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while (size > 0) {
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GPU::Write<u32>(reg_addr + 0x1EB00000, *src);
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size -= 4;
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++src;
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reg_addr += 4;
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}
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}
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/// Read a GSP GPU hardware register
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void ReadHWRegs(Service::Interface* self) {
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u32* cmd_buff = Service::GetCommandBuffer();
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u32 reg_addr = cmd_buff[1];
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u32 size = cmd_buff[2];
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// TODO: Return proper error codes
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if (reg_addr + size >= 0x420000) {
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ERROR_LOG(GPU, "Read address out of range! (address=0x%08x, size=0x%08x)", reg_addr, size);
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return;
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}
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// size should be word-aligned
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if ((size % 4) != 0) {
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ERROR_LOG(GPU, "Invalid size 0x%08x", size);
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return;
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}
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u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]);
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while (size > 0) {
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GPU::Read<u32>(*dst, reg_addr + 0x1EB00000);
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size -= 4;
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++dst;
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reg_addr += 4;
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}
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}
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/**
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@ -134,52 +153,92 @@ void RegisterInterruptRelayQueue(Service::Interface* self) {
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/// This triggers handling of the GX command written to the command buffer in shared memory.
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void TriggerCmdReqQueue(Service::Interface* self) {
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GX_CmdBufferHeader* header = (GX_CmdBufferHeader*)GX_GetCmdBufferPointer(g_thread_id);
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u32* cmd_buff = (u32*)GX_GetCmdBufferPointer(g_thread_id, 0x20 + (header->index * 0x20));
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switch (static_cast<GXCommandId>(cmd_buff[0])) {
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// Utility function to convert register ID to address
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auto WriteGPURegister = [](u32 id, u32 data) {
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GPU::Write<u32>(0x1EF00000 + 4 * id, data);
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};
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GX_CmdBufferHeader* header = (GX_CmdBufferHeader*)GX_GetCmdBufferPointer(g_thread_id);
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auto& command = *(const GXCommand*)GX_GetCmdBufferPointer(g_thread_id, 0x20 + (header->index * 0x20));
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switch (command.id) {
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// GX request DMA - typically used for copying memory from GSP heap to VRAM
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case GXCommandId::REQUEST_DMA:
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memcpy(Memory::GetPointer(cmd_buff[2]), Memory::GetPointer(cmd_buff[1]), cmd_buff[3]);
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memcpy(Memory::GetPointer(command.dma_request.dest_address),
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Memory::GetPointer(command.dma_request.source_address),
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command.dma_request.size);
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break;
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// ctrulib homebrew sends all relevant command list data with this command,
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// hence we do all "interesting" stuff here and do nothing in SET_COMMAND_LIST_FIRST.
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// TODO: This will need some rework in the future.
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case GXCommandId::SET_COMMAND_LIST_LAST:
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GPU::Write<u32>(GPU::Registers::CommandListAddress, cmd_buff[1] >> 3);
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GPU::Write<u32>(GPU::Registers::CommandListSize, cmd_buff[2] >> 3);
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GPU::Write<u32>(GPU::Registers::ProcessCommandList, 1); // TODO: Not sure if we are supposed to always write this
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{
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auto& params = command.set_command_list_last;
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WriteGPURegister(GPU::Regs::CommandProcessor + 2, params.address >> 3);
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WriteGPURegister(GPU::Regs::CommandProcessor, params.size >> 3);
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WriteGPURegister(GPU::Regs::CommandProcessor + 4, 1); // TODO: Not sure if we are supposed to always write this .. seems to trigger processing though
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// TODO: Move this to GPU
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// TODO: Not sure what units the size is measured in
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g_debugger.CommandListCalled(cmd_buff[1], (u32*)Memory::GetPointer(cmd_buff[1]), cmd_buff[2]);
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g_debugger.CommandListCalled(params.address,
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(u32*)Memory::GetPointer(params.address),
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params.size);
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break;
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}
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// It's assumed that the two "blocks" behave equivalently.
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// Presumably this is done simply to allow two memory fills to run in parallel.
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case GXCommandId::SET_MEMORY_FILL:
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break;
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{
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auto& params = command.memory_fill;
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WriteGPURegister(GPU::Regs::MemoryFill, params.start1 >> 3);
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WriteGPURegister(GPU::Regs::MemoryFill + 1, params.end1 >> 3);
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WriteGPURegister(GPU::Regs::MemoryFill + 2, params.end1 - params.start1);
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WriteGPURegister(GPU::Regs::MemoryFill + 3, params.value1);
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WriteGPURegister(GPU::Regs::MemoryFill + 4, params.start2 >> 3);
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WriteGPURegister(GPU::Regs::MemoryFill + 5, params.end2 >> 3);
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WriteGPURegister(GPU::Regs::MemoryFill + 6, params.end2 - params.start2);
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WriteGPURegister(GPU::Regs::MemoryFill + 7, params.value2);
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break;
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}
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// TODO: Check if texture copies are implemented correctly..
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case GXCommandId::SET_DISPLAY_TRANSFER:
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break;
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case GXCommandId::SET_TEXTURE_COPY:
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break;
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{
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auto& params = command.image_copy;
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WriteGPURegister(GPU::Regs::DisplayTransfer, params.in_buffer_address >> 3);
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WriteGPURegister(GPU::Regs::DisplayTransfer + 1, params.out_buffer_address >> 3);
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WriteGPURegister(GPU::Regs::DisplayTransfer + 3, params.in_buffer_size);
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WriteGPURegister(GPU::Regs::DisplayTransfer + 2, params.out_buffer_size);
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WriteGPURegister(GPU::Regs::DisplayTransfer + 4, params.flags);
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// TODO: Should this only be ORed with 1 for texture copies?
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// trigger transfer
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WriteGPURegister(GPU::Regs::DisplayTransfer + 6, 1);
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break;
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}
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// TODO: Figure out what exactly SET_COMMAND_LIST_FIRST and SET_COMMAND_LIST_LAST
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// are supposed to do.
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case GXCommandId::SET_COMMAND_LIST_FIRST:
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{
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//u32* buf0_data = (u32*)Memory::GetPointer(cmd_buff[1]);
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//u32* buf1_data = (u32*)Memory::GetPointer(cmd_buff[3]);
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//u32* buf2_data = (u32*)Memory::GetPointer(cmd_buff[5]);
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break;
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}
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default:
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ERROR_LOG(GSP, "unknown command 0x%08X", cmd_buff[0]);
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ERROR_LOG(GSP, "unknown command 0x%08X", (int)command.id.Value());
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}
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GX_FinishCommand(g_thread_id);
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}
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const Interface::FunctionInfo FunctionTable[] = {
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{0x00010082, nullptr, "WriteHWRegs"},
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{0x00010082, WriteHWRegs, "WriteHWRegs"},
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{0x00020084, nullptr, "WriteHWRegsWithMask"},
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{0x00030082, nullptr, "WriteHWRegRepeat"},
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{0x00040080, ReadHWRegs, "ReadHWRegs"},
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@ -4,6 +4,7 @@
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#pragma once
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#include "common/bit_field.h"
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#include "core/hle/service/service.h"
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////////////////////////////////////////////////////////////////////////////////////////////////////
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@ -12,21 +13,58 @@
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namespace GSP_GPU {
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enum class GXCommandId : u32 {
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REQUEST_DMA = 0x00000000,
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SET_COMMAND_LIST_LAST = 0x00000001,
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SET_MEMORY_FILL = 0x00000002, // TODO: Confirm? (lictru uses 0x01000102)
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SET_DISPLAY_TRANSFER = 0x00000003,
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SET_TEXTURE_COPY = 0x00000004,
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SET_COMMAND_LIST_FIRST = 0x00000005,
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REQUEST_DMA = 0x00,
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SET_COMMAND_LIST_LAST = 0x01,
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// Fills a given memory range with a particular value
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SET_MEMORY_FILL = 0x02,
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// Copies an image and optionally performs color-conversion or scaling.
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// This is highly similar to the GameCube's EFB copy feature
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SET_DISPLAY_TRANSFER = 0x03,
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// Conceptionally similar to SET_DISPLAY_TRANSFER and presumable uses the same hardware path
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SET_TEXTURE_COPY = 0x04,
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SET_COMMAND_LIST_FIRST = 0x05,
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};
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union GXCommand {
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struct GXCommand {
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BitField<0, 8, GXCommandId> id;
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union {
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struct {
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GXCommandId id;
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};
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u32 source_address;
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u32 dest_address;
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u32 size;
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} dma_request;
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u32 data[0x20];
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struct {
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u32 address;
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u32 size;
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} set_command_list_last;
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struct {
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u32 start1;
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u32 value1;
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u32 end1;
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u32 start2;
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u32 value2;
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u32 end2;
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} memory_fill;
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struct {
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u32 in_buffer_address;
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u32 out_buffer_address;
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u32 in_buffer_size;
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u32 out_buffer_size;
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u32 flags;
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} image_copy;
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u8 raw_data[0x1C];
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};
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};
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static_assert(sizeof(GXCommand) == 0x20, "GXCommand struct has incorrect size");
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/// Interface to "srv:" service
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class Interface : public Service::Interface {
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@ -15,7 +15,7 @@
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namespace GPU {
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Registers g_regs;
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RegisterSet<u32, Regs> g_regs;
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u64 g_last_ticks = 0; ///< Last CPU ticks
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@ -26,37 +26,47 @@ u64 g_last_ticks = 0; ///< Last CPU ticks
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void SetFramebufferLocation(const FramebufferLocation mode) {
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switch (mode) {
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case FRAMEBUFFER_LOCATION_FCRAM:
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g_regs.framebuffer_top_left_1 = PADDR_TOP_LEFT_FRAME1;
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g_regs.framebuffer_top_left_2 = PADDR_TOP_LEFT_FRAME2;
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g_regs.framebuffer_top_right_1 = PADDR_TOP_RIGHT_FRAME1;
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g_regs.framebuffer_top_right_2 = PADDR_TOP_RIGHT_FRAME2;
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g_regs.framebuffer_sub_left_1 = PADDR_SUB_FRAME1;
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//g_regs.framebuffer_sub_left_2 = unknown;
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g_regs.framebuffer_sub_right_1 = PADDR_SUB_FRAME2;
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//g_regs.framebufferr_sub_right_2 = unknown;
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{
|
||||
auto& framebuffer_top = g_regs.Get<Regs::FramebufferTop>();
|
||||
auto& framebuffer_sub = g_regs.Get<Regs::FramebufferBottom>();
|
||||
|
||||
framebuffer_top.address_left1 = PADDR_TOP_LEFT_FRAME1;
|
||||
framebuffer_top.address_left2 = PADDR_TOP_LEFT_FRAME2;
|
||||
framebuffer_top.address_right1 = PADDR_TOP_RIGHT_FRAME1;
|
||||
framebuffer_top.address_right2 = PADDR_TOP_RIGHT_FRAME2;
|
||||
framebuffer_sub.address_left1 = PADDR_SUB_FRAME1;
|
||||
//framebuffer_sub.address_left2 = unknown;
|
||||
framebuffer_sub.address_right1 = PADDR_SUB_FRAME2;
|
||||
//framebuffer_sub.address_right2 = unknown;
|
||||
break;
|
||||
}
|
||||
|
||||
case FRAMEBUFFER_LOCATION_VRAM:
|
||||
g_regs.framebuffer_top_left_1 = PADDR_VRAM_TOP_LEFT_FRAME1;
|
||||
g_regs.framebuffer_top_left_2 = PADDR_VRAM_TOP_LEFT_FRAME2;
|
||||
g_regs.framebuffer_top_right_1 = PADDR_VRAM_TOP_RIGHT_FRAME1;
|
||||
g_regs.framebuffer_top_right_2 = PADDR_VRAM_TOP_RIGHT_FRAME2;
|
||||
g_regs.framebuffer_sub_left_1 = PADDR_VRAM_SUB_FRAME1;
|
||||
//g_regs.framebuffer_sub_left_2 = unknown;
|
||||
g_regs.framebuffer_sub_right_1 = PADDR_VRAM_SUB_FRAME2;
|
||||
//g_regs.framebufferr_sub_right_2 = unknown;
|
||||
{
|
||||
auto& framebuffer_top = g_regs.Get<Regs::FramebufferTop>();
|
||||
auto& framebuffer_sub = g_regs.Get<Regs::FramebufferBottom>();
|
||||
|
||||
framebuffer_top.address_left1 = PADDR_VRAM_TOP_LEFT_FRAME1;
|
||||
framebuffer_top.address_left2 = PADDR_VRAM_TOP_LEFT_FRAME2;
|
||||
framebuffer_top.address_right1 = PADDR_VRAM_TOP_RIGHT_FRAME1;
|
||||
framebuffer_top.address_right2 = PADDR_VRAM_TOP_RIGHT_FRAME2;
|
||||
framebuffer_sub.address_left1 = PADDR_VRAM_SUB_FRAME1;
|
||||
//framebuffer_sub.address_left2 = unknown;
|
||||
framebuffer_sub.address_right1 = PADDR_VRAM_SUB_FRAME2;
|
||||
//framebuffer_sub.address_right2 = unknown;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Gets the location of the framebuffers
|
||||
* @return Location of framebuffers as FramebufferLocation enum
|
||||
*/
|
||||
const FramebufferLocation GetFramebufferLocation() {
|
||||
if ((g_regs.framebuffer_top_right_1 & ~Memory::VRAM_MASK) == Memory::VRAM_PADDR) {
|
||||
FramebufferLocation GetFramebufferLocation(u32 address) {
|
||||
if ((address & ~Memory::VRAM_MASK) == Memory::VRAM_PADDR) {
|
||||
return FRAMEBUFFER_LOCATION_VRAM;
|
||||
} else if ((g_regs.framebuffer_top_right_1 & ~Memory::FCRAM_MASK) == Memory::FCRAM_PADDR) {
|
||||
} else if ((address & ~Memory::FCRAM_MASK) == Memory::FCRAM_PADDR) {
|
||||
return FRAMEBUFFER_LOCATION_FCRAM;
|
||||
} else {
|
||||
ERROR_LOG(GPU, "unknown framebuffer location!");
|
||||
|
|
@ -64,91 +74,161 @@ const FramebufferLocation GetFramebufferLocation() {
|
|||
return FRAMEBUFFER_LOCATION_UNKNOWN;
|
||||
}
|
||||
|
||||
u32 GetFramebufferAddr(const u32 address) {
|
||||
switch (GetFramebufferLocation(address)) {
|
||||
case FRAMEBUFFER_LOCATION_FCRAM:
|
||||
return Memory::VirtualAddressFromPhysical_FCRAM(address);
|
||||
case FRAMEBUFFER_LOCATION_VRAM:
|
||||
return Memory::VirtualAddressFromPhysical_VRAM(address);
|
||||
default:
|
||||
ERROR_LOG(GPU, "unknown framebuffer location");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Gets a read-only pointer to a framebuffer in memory
|
||||
* @param address Physical address of framebuffer
|
||||
* @return Returns const pointer to raw framebuffer
|
||||
*/
|
||||
const u8* GetFramebufferPointer(const u32 address) {
|
||||
switch (GetFramebufferLocation()) {
|
||||
case FRAMEBUFFER_LOCATION_FCRAM:
|
||||
return (const u8*)Memory::GetPointer(Memory::VirtualAddressFromPhysical_FCRAM(address));
|
||||
case FRAMEBUFFER_LOCATION_VRAM:
|
||||
return (const u8*)Memory::GetPointer(Memory::VirtualAddressFromPhysical_VRAM(address));
|
||||
default:
|
||||
ERROR_LOG(GPU, "unknown framebuffer location");
|
||||
}
|
||||
return NULL;
|
||||
u32 addr = GetFramebufferAddr(address);
|
||||
return (addr != 0) ? Memory::GetPointer(addr) : nullptr;
|
||||
}
|
||||
|
||||
template <typename T>
|
||||
inline void Read(T &var, const u32 addr) {
|
||||
switch (addr) {
|
||||
case Registers::FramebufferTopLeft1:
|
||||
var = g_regs.framebuffer_top_left_1;
|
||||
break;
|
||||
inline void Read(T &var, const u32 raw_addr) {
|
||||
u32 addr = raw_addr - 0x1EF00000;
|
||||
int index = addr / 4;
|
||||
|
||||
case Registers::FramebufferTopLeft2:
|
||||
var = g_regs.framebuffer_top_left_2;
|
||||
break;
|
||||
|
||||
case Registers::FramebufferTopRight1:
|
||||
var = g_regs.framebuffer_top_right_1;
|
||||
break;
|
||||
|
||||
case Registers::FramebufferTopRight2:
|
||||
var = g_regs.framebuffer_top_right_2;
|
||||
break;
|
||||
|
||||
case Registers::FramebufferSubLeft1:
|
||||
var = g_regs.framebuffer_sub_left_1;
|
||||
break;
|
||||
|
||||
case Registers::FramebufferSubRight1:
|
||||
var = g_regs.framebuffer_sub_right_1;
|
||||
break;
|
||||
|
||||
case Registers::CommandListSize:
|
||||
var = g_regs.command_list_size;
|
||||
break;
|
||||
|
||||
case Registers::CommandListAddress:
|
||||
var = g_regs.command_list_address;
|
||||
break;
|
||||
|
||||
case Registers::ProcessCommandList:
|
||||
var = g_regs.command_processing_enabled;
|
||||
break;
|
||||
|
||||
default:
|
||||
// Reads other than u32 are untested, so I'd rather have them abort than silently fail
|
||||
if (index >= Regs::NumIds || !std::is_same<T,u32>::value)
|
||||
{
|
||||
ERROR_LOG(GPU, "unknown Read%d @ 0x%08X", sizeof(var) * 8, addr);
|
||||
break;
|
||||
return;
|
||||
}
|
||||
|
||||
var = g_regs[static_cast<Regs::Id>(addr / 4)];
|
||||
}
|
||||
|
||||
template <typename T>
|
||||
inline void Write(u32 addr, const T data) {
|
||||
switch (static_cast<Registers::Id>(addr)) {
|
||||
case Registers::CommandListSize:
|
||||
g_regs.command_list_size = data;
|
||||
break;
|
||||
addr -= 0x1EF00000;
|
||||
int index = addr / 4;
|
||||
|
||||
case Registers::CommandListAddress:
|
||||
g_regs.command_list_address = data;
|
||||
break;
|
||||
|
||||
case Registers::ProcessCommandList:
|
||||
g_regs.command_processing_enabled = data;
|
||||
if (g_regs.command_processing_enabled & 1)
|
||||
// Writes other than u32 are untested, so I'd rather have them abort than silently fail
|
||||
if (index >= Regs::NumIds || !std::is_same<T,u32>::value)
|
||||
{
|
||||
// u32* buffer = (u32*)Memory::GetPointer(g_regs.command_list_address << 3);
|
||||
ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", g_regs.command_list_size, g_regs.command_list_address << 3);
|
||||
ERROR_LOG(GPU, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr);
|
||||
return;
|
||||
}
|
||||
|
||||
g_regs[static_cast<Regs::Id>(index)] = data;
|
||||
|
||||
switch (static_cast<Regs::Id>(index)) {
|
||||
|
||||
// Memory fills are triggered once the fill value is written.
|
||||
// NOTE: This is not verified.
|
||||
case Regs::MemoryFill + 3:
|
||||
case Regs::MemoryFill + 7:
|
||||
{
|
||||
const auto& config = g_regs.Get<Regs::MemoryFill>(static_cast<Regs::Id>(index - 3));
|
||||
|
||||
// TODO: Not sure if this check should be done at GSP level instead
|
||||
if (config.address_start) {
|
||||
// TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all
|
||||
u32* start = (u32*)Memory::GetPointer(config.GetStartAddress());
|
||||
u32* end = (u32*)Memory::GetPointer(config.GetEndAddress());
|
||||
for (u32* ptr = start; ptr < end; ++ptr)
|
||||
*ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation
|
||||
|
||||
DEBUG_LOG(GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(), config.GetEndAddress());
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case Regs::DisplayTransfer + 6:
|
||||
{
|
||||
const auto& config = g_regs.Get<Regs::DisplayTransfer>();
|
||||
if (config.trigger & 1) {
|
||||
u8* source_pointer = Memory::GetPointer(config.GetPhysicalInputAddress());
|
||||
u8* dest_pointer = Memory::GetPointer(config.GetPhysicalOutputAddress());
|
||||
|
||||
for (int y = 0; y < config.output_height; ++y) {
|
||||
// TODO: Why does the register seem to hold twice the framebuffer width?
|
||||
for (int x = 0; x < config.output_width / 2; ++x) {
|
||||
struct {
|
||||
int r, g, b, a;
|
||||
} source_color = { 0, 0, 0, 0 };
|
||||
|
||||
switch (config.input_format) {
|
||||
case Regs::FramebufferFormat::RGBA8:
|
||||
{
|
||||
// TODO: Most likely got the component order messed up.
|
||||
u8* srcptr = source_pointer + x * 4 + y * config.input_width * 4 / 2;
|
||||
source_color.r = srcptr[0]; // blue
|
||||
source_color.g = srcptr[1]; // green
|
||||
source_color.b = srcptr[2]; // red
|
||||
source_color.a = srcptr[3]; // alpha
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
ERROR_LOG(GPU, "Unknown source framebuffer format %x", config.input_format.Value());
|
||||
break;
|
||||
}
|
||||
|
||||
switch (config.output_format) {
|
||||
/*case Regs::FramebufferFormat::RGBA8:
|
||||
{
|
||||
// TODO: Untested
|
||||
u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.output_width * 4);
|
||||
dstptr[0] = source_color.r;
|
||||
dstptr[1] = source_color.g;
|
||||
dstptr[2] = source_color.b;
|
||||
dstptr[3] = source_color.a;
|
||||
break;
|
||||
}*/
|
||||
|
||||
case Regs::FramebufferFormat::RGB8:
|
||||
{
|
||||
// TODO: Most likely got the component order messed up.
|
||||
u8* dstptr = dest_pointer + x * 3 + y * config.output_width * 3 / 2;
|
||||
dstptr[0] = source_color.r; // blue
|
||||
dstptr[1] = source_color.g; // green
|
||||
dstptr[2] = source_color.b; // red
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
ERROR_LOG(GPU, "Unknown destination framebuffer format %x", config.output_format.Value());
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DEBUG_LOG(GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%dx%d)-> 0x%08x(%dx%d), dst format %x",
|
||||
config.output_height * config.output_width * 4,
|
||||
config.GetPhysicalInputAddress(), (int)config.input_width, (int)config.input_height,
|
||||
config.GetPhysicalOutputAddress(), (int)config.output_width, (int)config.output_height,
|
||||
config.output_format.Value());
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case Regs::CommandProcessor + 4:
|
||||
{
|
||||
const auto& config = g_regs.Get<Regs::CommandProcessor>();
|
||||
if (config.trigger & 1)
|
||||
{
|
||||
// u32* buffer = (u32*)Memory::GetPointer(config.address << 3);
|
||||
ERROR_LOG(GPU, "Beginning 0x%08x bytes of commands from address 0x%08x", config.size, config.address << 3);
|
||||
// TODO: Process command list!
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
ERROR_LOG(GPU, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -180,7 +260,24 @@ void Update() {
|
|||
/// Initialize hardware
|
||||
void Init() {
|
||||
g_last_ticks = Core::g_app_core->GetTicks();
|
||||
SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM);
|
||||
// SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM);
|
||||
SetFramebufferLocation(FRAMEBUFFER_LOCATION_VRAM);
|
||||
|
||||
auto& framebuffer_top = g_regs.Get<Regs::FramebufferTop>();
|
||||
auto& framebuffer_sub = g_regs.Get<Regs::FramebufferBottom>();
|
||||
// TODO: Width should be 240 instead?
|
||||
framebuffer_top.width = 480;
|
||||
framebuffer_top.height = 400;
|
||||
framebuffer_top.stride = 480*3;
|
||||
framebuffer_top.color_format = Regs::FramebufferFormat::RGB8;
|
||||
framebuffer_top.active_fb = 0;
|
||||
|
||||
framebuffer_sub.width = 480;
|
||||
framebuffer_sub.height = 400;
|
||||
framebuffer_sub.stride = 480*3;
|
||||
framebuffer_sub.color_format = Regs::FramebufferFormat::RGB8;
|
||||
framebuffer_sub.active_fb = 0;
|
||||
|
||||
NOTICE_LOG(GPU, "initialized OK");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -5,43 +5,168 @@
|
|||
#pragma once
|
||||
|
||||
#include "common/common_types.h"
|
||||
#include "common/bit_field.h"
|
||||
#include "common/register_set.h"
|
||||
|
||||
namespace GPU {
|
||||
|
||||
static const u32 kFrameCycles = 268123480 / 60; ///< 268MHz / 60 frames per second
|
||||
static const u32 kFrameTicks = kFrameCycles / 3; ///< Approximate number of instructions/frame
|
||||
|
||||
struct Registers {
|
||||
// MMIO region 0x1EFxxxxx
|
||||
struct Regs {
|
||||
enum Id : u32 {
|
||||
FramebufferTopLeft1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left
|
||||
FramebufferTopLeft2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left
|
||||
FramebufferTopRight1 = 0x1EF00494, // Main LCD, first framebuffer for 3D right
|
||||
FramebufferTopRight2 = 0x1EF00498, // Main LCD, second framebuffer for 3D right
|
||||
FramebufferSubLeft1 = 0x1EF00568, // Sub LCD, first framebuffer
|
||||
FramebufferSubLeft2 = 0x1EF0056C, // Sub LCD, second framebuffer
|
||||
FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer
|
||||
FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer
|
||||
MemoryFill = 0x00004, // + 5,6,7; second block at 8-11
|
||||
|
||||
CommandListSize = 0x1EF018E0,
|
||||
CommandListAddress = 0x1EF018E8,
|
||||
ProcessCommandList = 0x1EF018F0,
|
||||
FramebufferTop = 0x00117, // + 11a,11b,11c,11d(?),11e...126
|
||||
FramebufferBottom = 0x00157, // + 15a,15b,15c,15d(?),15e...166
|
||||
|
||||
DisplayTransfer = 0x00300, // + 301,302,303,304,305,306
|
||||
|
||||
CommandProcessor = 0x00638, // + 63a,63c
|
||||
|
||||
NumIds = 0x01000
|
||||
};
|
||||
|
||||
u32 framebuffer_top_left_1;
|
||||
u32 framebuffer_top_left_2;
|
||||
u32 framebuffer_top_right_1;
|
||||
u32 framebuffer_top_right_2;
|
||||
u32 framebuffer_sub_left_1;
|
||||
u32 framebuffer_sub_left_2;
|
||||
u32 framebuffer_sub_right_1;
|
||||
u32 framebuffer_sub_right_2;
|
||||
template<Id id>
|
||||
struct Struct;
|
||||
|
||||
u32 command_list_size;
|
||||
u32 command_list_address;
|
||||
u32 command_processing_enabled;
|
||||
enum class FramebufferFormat : u32 {
|
||||
RGBA8 = 0,
|
||||
RGB8 = 1,
|
||||
RGB565 = 2,
|
||||
RGB5A1 = 3,
|
||||
RGBA4 = 4,
|
||||
};
|
||||
};
|
||||
|
||||
extern Registers g_regs;
|
||||
template<>
|
||||
struct Regs::Struct<Regs::MemoryFill> {
|
||||
u32 address_start;
|
||||
u32 address_end; // ?
|
||||
u32 size;
|
||||
u32 value; // ?
|
||||
|
||||
inline u32 GetStartAddress() const {
|
||||
return address_start * 8;
|
||||
}
|
||||
|
||||
inline u32 GetEndAddress() const {
|
||||
return address_end * 8;
|
||||
}
|
||||
};
|
||||
static_assert(sizeof(Regs::Struct<Regs::MemoryFill>) == 0x10, "Structure size and register block length don't match");
|
||||
|
||||
template<>
|
||||
struct Regs::Struct<Regs::FramebufferTop> {
|
||||
using Format = Regs::FramebufferFormat;
|
||||
|
||||
union {
|
||||
u32 size;
|
||||
|
||||
BitField< 0, 16, u32> width;
|
||||
BitField<16, 16, u32> height;
|
||||
};
|
||||
|
||||
u32 pad0[2];
|
||||
|
||||
u32 address_left1;
|
||||
u32 address_left2;
|
||||
|
||||
union {
|
||||
u32 format;
|
||||
|
||||
BitField< 0, 3, Format> color_format;
|
||||
};
|
||||
|
||||
u32 pad1;
|
||||
|
||||
union {
|
||||
u32 active_fb;
|
||||
|
||||
// 0: Use parameters ending with "1"
|
||||
// 1: Use parameters ending with "2"
|
||||
BitField<0, 1, u32> second_fb_active;
|
||||
};
|
||||
|
||||
u32 pad2[5];
|
||||
|
||||
// Distance between two pixel rows, in bytes
|
||||
u32 stride;
|
||||
|
||||
u32 address_right1;
|
||||
u32 address_right2;
|
||||
};
|
||||
|
||||
template<>
|
||||
struct Regs::Struct<Regs::FramebufferBottom> : public Regs::Struct<Regs::FramebufferTop> {
|
||||
};
|
||||
static_assert(sizeof(Regs::Struct<Regs::FramebufferTop>) == 0x40, "Structure size and register block length don't match");
|
||||
|
||||
template<>
|
||||
struct Regs::Struct<Regs::DisplayTransfer> {
|
||||
using Format = Regs::FramebufferFormat;
|
||||
|
||||
u32 input_address;
|
||||
u32 output_address;
|
||||
|
||||
inline u32 GetPhysicalInputAddress() const {
|
||||
return input_address * 8;
|
||||
}
|
||||
|
||||
inline u32 GetPhysicalOutputAddress() const {
|
||||
return output_address * 8;
|
||||
}
|
||||
|
||||
union {
|
||||
u32 output_size;
|
||||
|
||||
BitField< 0, 16, u32> output_width;
|
||||
BitField<16, 16, u32> output_height;
|
||||
};
|
||||
|
||||
union {
|
||||
u32 input_size;
|
||||
|
||||
BitField< 0, 16, u32> input_width;
|
||||
BitField<16, 16, u32> input_height;
|
||||
};
|
||||
|
||||
union {
|
||||
u32 flags;
|
||||
|
||||
BitField< 0, 1, u32> flip_data; // flips input data horizontally (TODO) if true
|
||||
BitField< 8, 3, Format> input_format;
|
||||
BitField<12, 3, Format> output_format;
|
||||
BitField<16, 1, u32> output_tiled; // stores output in a tiled format
|
||||
};
|
||||
|
||||
u32 unknown;
|
||||
|
||||
// it seems that writing to this field triggers the display transfer
|
||||
u32 trigger;
|
||||
};
|
||||
static_assert(sizeof(Regs::Struct<Regs::DisplayTransfer>) == 0x1C, "Structure size and register block length don't match");
|
||||
|
||||
template<>
|
||||
struct Regs::Struct<Regs::CommandProcessor> {
|
||||
// command list size
|
||||
u32 size;
|
||||
|
||||
u32 pad0;
|
||||
|
||||
// command list address
|
||||
u32 address;
|
||||
|
||||
u32 pad1;
|
||||
|
||||
// it seems that writing to this field triggers command list processing
|
||||
u32 trigger;
|
||||
};
|
||||
static_assert(sizeof(Regs::Struct<Regs::CommandProcessor>) == 0x14, "Structure size and register block length don't match");
|
||||
|
||||
|
||||
extern RegisterSet<u32, Regs> g_regs;
|
||||
|
||||
enum {
|
||||
TOP_ASPECT_X = 0x5,
|
||||
|
|
@ -51,23 +176,35 @@ enum {
|
|||
TOP_WIDTH = 400,
|
||||
BOTTOM_WIDTH = 320,
|
||||
|
||||
// Physical addresses in FCRAM used by ARM9 applications - these are correct for real hardware
|
||||
PADDR_FRAMEBUFFER_SEL = 0x20184E59,
|
||||
PADDR_TOP_LEFT_FRAME1 = 0x20184E60,
|
||||
// Physical addresses in FCRAM (chosen arbitrarily)
|
||||
PADDR_TOP_LEFT_FRAME1 = 0x201D4C00,
|
||||
PADDR_TOP_LEFT_FRAME2 = 0x202D4C00,
|
||||
PADDR_TOP_RIGHT_FRAME1 = 0x203D4C00,
|
||||
PADDR_TOP_RIGHT_FRAME2 = 0x204D4C00,
|
||||
PADDR_SUB_FRAME1 = 0x205D4C00,
|
||||
PADDR_SUB_FRAME2 = 0x206D4C00,
|
||||
// Physical addresses in FCRAM used by ARM9 applications
|
||||
/* PADDR_TOP_LEFT_FRAME1 = 0x20184E60,
|
||||
PADDR_TOP_LEFT_FRAME2 = 0x201CB370,
|
||||
PADDR_TOP_RIGHT_FRAME1 = 0x20282160,
|
||||
PADDR_TOP_RIGHT_FRAME2 = 0x202C8670,
|
||||
PADDR_SUB_FRAME1 = 0x202118E0,
|
||||
PADDR_SUB_FRAME2 = 0x20249CF0,
|
||||
PADDR_SUB_FRAME2 = 0x20249CF0,*/
|
||||
|
||||
// Physical addresses in VRAM - I'm not sure how these are actually allocated (so not real)
|
||||
PADDR_VRAM_FRAMEBUFFER_SEL = 0x18184E59,
|
||||
PADDR_VRAM_TOP_LEFT_FRAME1 = 0x18184E60,
|
||||
PADDR_VRAM_TOP_LEFT_FRAME2 = 0x181CB370,
|
||||
// Physical addresses in VRAM
|
||||
// TODO: These should just be deduced from the ones above
|
||||
PADDR_VRAM_TOP_LEFT_FRAME1 = 0x181D4C00,
|
||||
PADDR_VRAM_TOP_LEFT_FRAME2 = 0x182D4C00,
|
||||
PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x183D4C00,
|
||||
PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x184D4C00,
|
||||
PADDR_VRAM_SUB_FRAME1 = 0x185D4C00,
|
||||
PADDR_VRAM_SUB_FRAME2 = 0x186D4C00,
|
||||
// Physical addresses in VRAM used by ARM9 applications
|
||||
/* PADDR_VRAM_TOP_LEFT_FRAME2 = 0x181CB370,
|
||||
PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x18282160,
|
||||
PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x182C8670,
|
||||
PADDR_VRAM_SUB_FRAME1 = 0x182118E0,
|
||||
PADDR_VRAM_SUB_FRAME2 = 0x18249CF0,
|
||||
PADDR_VRAM_SUB_FRAME2 = 0x18249CF0,*/
|
||||
};
|
||||
|
||||
/// Framebuffer location
|
||||
|
|
@ -90,16 +227,18 @@ void SetFramebufferLocation(const FramebufferLocation mode);
|
|||
*/
|
||||
const u8* GetFramebufferPointer(const u32 address);
|
||||
|
||||
u32 GetFramebufferAddr(const u32 address);
|
||||
|
||||
/**
|
||||
* Gets the location of the framebuffers
|
||||
*/
|
||||
const FramebufferLocation GetFramebufferLocation();
|
||||
FramebufferLocation GetFramebufferLocation(u32 address);
|
||||
|
||||
template <typename T>
|
||||
inline void Read(T &var, const u32 addr);
|
||||
void Read(T &var, const u32 addr);
|
||||
|
||||
template <typename T>
|
||||
inline void Write(u32 addr, const T data);
|
||||
void Write(u32 addr, const T data);
|
||||
|
||||
/// Update hardware
|
||||
void Update();
|
||||
|
|
|
|||
|
|
@ -9,10 +9,10 @@
|
|||
namespace HW {
|
||||
|
||||
template <typename T>
|
||||
inline void Read(T &var, const u32 addr);
|
||||
void Read(T &var, const u32 addr);
|
||||
|
||||
template <typename T>
|
||||
inline void Write(u32 addr, const T data);
|
||||
void Write(u32 addr, const T data);
|
||||
|
||||
/// Update hardware
|
||||
void Update();
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ public:
|
|||
virtual void GXCommandProcessed(int total_command_count)
|
||||
{
|
||||
const GSP_GPU::GXCommand& cmd = observed->ReadGXCommandHistory(total_command_count-1);
|
||||
ERROR_LOG(GSP, "Received command: id=%x", cmd.id);
|
||||
ERROR_LOG(GSP, "Received command: id=%x", (int)cmd.id.Value());
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -78,11 +78,13 @@ public:
|
|||
|
||||
void GXCommandProcessed(u8* command_data)
|
||||
{
|
||||
if (observers.empty())
|
||||
return;
|
||||
|
||||
gx_command_history.push_back(GSP_GPU::GXCommand());
|
||||
GSP_GPU::GXCommand& cmd = gx_command_history[gx_command_history.size()-1];
|
||||
|
||||
const int cmd_length = sizeof(GSP_GPU::GXCommand);
|
||||
memcpy(cmd.data, command_data, cmd_length);
|
||||
memcpy(&cmd, command_data, sizeof(GSP_GPU::GXCommand));
|
||||
|
||||
ForEachObserver([this](DebuggerObserver* observer) {
|
||||
observer->GXCommandProcessed(this->gx_command_history.size());
|
||||
|
|
@ -91,6 +93,9 @@ public:
|
|||
|
||||
void CommandListCalled(u32 address, u32* command_list, u32 size_in_words)
|
||||
{
|
||||
if (observers.empty())
|
||||
return;
|
||||
|
||||
PicaCommandList cmdlist;
|
||||
for (u32* parse_pointer = command_list; parse_pointer < command_list + size_in_words;)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -61,10 +61,11 @@ void RendererOpenGL::FlipFramebuffer(const u8* in, u8* out) {
|
|||
int in_coord = 0;
|
||||
for (int x = 0; x < VideoCore::kScreenTopWidth; x++) {
|
||||
for (int y = VideoCore::kScreenTopHeight-1; y >= 0; y--) {
|
||||
// TODO: Properly support other framebuffer formats
|
||||
int out_coord = (x + y * VideoCore::kScreenTopWidth) * 3;
|
||||
out[out_coord] = in[in_coord];
|
||||
out[out_coord + 1] = in[in_coord + 1];
|
||||
out[out_coord + 2] = in[in_coord + 2];
|
||||
out[out_coord] = in[in_coord]; // blue?
|
||||
out[out_coord + 1] = in[in_coord + 1]; // green?
|
||||
out[out_coord + 2] = in[in_coord + 2]; // red?
|
||||
in_coord+=3;
|
||||
}
|
||||
}
|
||||
|
|
@ -77,8 +78,23 @@ void RendererOpenGL::FlipFramebuffer(const u8* in, u8* out) {
|
|||
*/
|
||||
void RendererOpenGL::RenderXFB(const common::Rect& src_rect, const common::Rect& dst_rect) {
|
||||
|
||||
FlipFramebuffer(GPU::GetFramebufferPointer(GPU::g_regs.framebuffer_top_left_1), m_xfb_top_flipped);
|
||||
FlipFramebuffer(GPU::GetFramebufferPointer(GPU::g_regs.framebuffer_sub_left_1), m_xfb_bottom_flipped);
|
||||
const auto& framebuffer_top = GPU::g_regs.Get<GPU::Regs::FramebufferTop>();
|
||||
const auto& framebuffer_sub = GPU::g_regs.Get<GPU::Regs::FramebufferBottom>();
|
||||
const u32 active_fb_top = (framebuffer_top.active_fb == 1)
|
||||
? framebuffer_top.address_left2
|
||||
: framebuffer_top.address_left1;
|
||||
const u32 active_fb_sub = (framebuffer_sub.active_fb == 1)
|
||||
? framebuffer_sub.address_left2
|
||||
: framebuffer_sub.address_left1;
|
||||
|
||||
DEBUG_LOG(GPU, "RenderXFB: 0x%08x bytes from 0x%08x(%dx%d), fmt %x",
|
||||
framebuffer_top.stride * framebuffer_top.height,
|
||||
GPU::GetFramebufferAddr(active_fb_top), (int)framebuffer_top.width,
|
||||
(int)framebuffer_top.height, (int)framebuffer_top.format);
|
||||
|
||||
// TODO: This should consider the GPU registers for framebuffer width, height and stride.
|
||||
FlipFramebuffer(GPU::GetFramebufferPointer(active_fb_top), m_xfb_top_flipped);
|
||||
FlipFramebuffer(GPU::GetFramebufferPointer(active_fb_sub), m_xfb_bottom_flipped);
|
||||
|
||||
// Blit the top framebuffer
|
||||
// ------------------------
|
||||
|
|
@ -110,7 +126,7 @@ void RendererOpenGL::RenderXFB(const common::Rect& src_rect, const common::Rect&
|
|||
// Update textures with contents of XFB in RAM - bottom
|
||||
glBindTexture(GL_TEXTURE_2D, m_xfb_texture_bottom);
|
||||
glTexSubImage2D(GL_TEXTURE_2D, 0, 0, 0, VideoCore::kScreenTopWidth, VideoCore::kScreenTopHeight,
|
||||
GL_RGB, GL_UNSIGNED_BYTE, m_xfb_bottom_flipped);
|
||||
GL_BGR, GL_UNSIGNED_BYTE, m_xfb_bottom_flipped);
|
||||
glBindTexture(GL_TEXTURE_2D, 0);
|
||||
|
||||
// Render target is destination framebuffer
|
||||
|
|
|
|||
|
|
@ -84,7 +84,6 @@ private:
|
|||
// "Flipped" framebuffers translate scanlines from native 3DS left-to-right to top-to-bottom
|
||||
// as OpenGL expects them in a texture. There probably is a more efficient way of doing this:
|
||||
|
||||
u8 m_xfb_top_flipped[VideoCore::kScreenTopWidth * VideoCore::kScreenTopWidth * 4];
|
||||
u8 m_xfb_bottom_flipped[VideoCore::kScreenTopWidth * VideoCore::kScreenTopWidth * 4];
|
||||
|
||||
u8 m_xfb_top_flipped[VideoCore::kScreenTopWidth * VideoCore::kScreenTopHeight * 4];
|
||||
u8 m_xfb_bottom_flipped[VideoCore::kScreenBottomWidth * VideoCore::kScreenBottomHeight * 4];
|
||||
};
|
||||
Loading…
Add table
Add a link
Reference in a new issue