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dyncom: Implemented LDREXD/STREXD/LDREXH/STREXH
This commit is contained in:
bunnei
parent
3b2da87080
commit
dd8a57cb80
3 changed files with 276 additions and 221 deletions
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@ -136,7 +136,6 @@ const ISEITEM arm_instruction[] = {
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{ "pkhbt", 2, 6, 20, 27, 0x00000068, 4, 6, 0x00000001 },
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{ "smul", 3, 4, 20, 27, 0x00000016, 7, 7, 0x00000001, 4, 4, 0x00000000 },
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{ "smlalxy", 3, 4, 20, 27, 0x00000014, 7, 7, 0x00000001, 4, 4, 0x00000000 },
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// {"smlal" , 2 , 4 , 21, 27, 0x00000007, 4, 7, 0x00000009},
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{ "smla", 3, 4, 20, 27, 0x00000010, 7, 7, 0x00000001, 4, 4, 0x00000000 },
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{ "mcrr", 1, 6, 20, 27, 0x000000c4 },
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{ "mrrc", 1, 6, 20, 27, 0x000000c5 },
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@ -194,6 +193,10 @@ const ISEITEM arm_instruction[] = {
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{ "ldc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000001 },
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{ "swi", 1, 0, 24, 27, 0x0000000f },
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{ "bbl", 1, 0, 25, 27, 0x00000005 },
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{ "ldrexd", 2, ARMV6K, 20, 27, 0x0000001B, 4, 7, 0x00000009 },
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{ "strexd", 2, ARMV6K, 20, 27, 0x0000001A, 4, 7, 0x00000009 },
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{ "ldrexh", 2, ARMV6K, 20, 27, 0x0000001F, 4, 7, 0x00000009 },
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{ "strexh", 2, ARMV6K, 20, 27, 0x0000001E, 4, 7, 0x00000009 },
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};
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const ISEITEM arm_exclusion_code[] = {
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@ -383,6 +386,11 @@ const ISEITEM arm_exclusion_code[] = {
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{ "ldc", 0, 0, 0 },
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{ "swi", 0, 0, 0 },
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{ "bbl", 0, 0, 0 },
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{ "ldrexd", 0, ARMV6K, 0 },
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{ "strexd", 0, ARMV6K, 0 },
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{ "ldrexh", 0, ARMV6K, 0 },
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{ "strexh", 0, ARMV6K, 0 },
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{ "bl_1_thumb", 0, INVALID, 0 }, // Should be table[-4]
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{ "bl_2_thumb", 0, INVALID, 0 }, // Should be located at the end of the table[-3]
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{ "blx_1_thumb", 0, INVALID, 0 }, // Should be located at table[-2]
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@ -395,6 +403,7 @@ int decode_arm_instr(uint32_t instr, int32_t *idx) {
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int ret = DECODE_FAILURE;
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int i = 0;
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int instr_slots = sizeof(arm_instruction) / sizeof(ISEITEM);
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for (i = 0; i < instr_slots; i++) {
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n = arm_instruction[i].attribute_value;
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base = 0;
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@ -1,153 +1,117 @@
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/* Copyright (C)
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* 2012 - Michael.Kang blackfin.kang@gmail.com
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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*/
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// Copyright 2012 Michael Kang, 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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/**
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* @file arm_dyncom_dec.h
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* @brief Some common utility for arm instruction decoder
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* @author Michael.Kang blackfin.kang@gmail.com
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* @version 7849
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* @date 2012-03-15
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*/
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#pragma once
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#ifndef __ARM_DYNCOM_DEC__
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#define __ARM_DYNCOM_DEC__
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#define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1))
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#define BIT(n) ((instr >> (n)) & 1)
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#define BAD do { printf("meet BAD at %s, instr is %x\n", __FUNCTION__, instr ); } while(0);
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#define ptr_N cpu->ptr_N
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#define ptr_Z cpu->ptr_Z
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#define ptr_C cpu->ptr_C
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#define ptr_V cpu->ptr_V
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#define ptr_I cpu->ptr_I
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#define ptr_T cpu->ptr_T
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#define ptr_CPSR cpu->ptr_gpr[16]
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#define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1))
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#define BIT(n) ((instr >> (n)) & 1)
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#define BAD do{printf("meet BAD at %s, instr is %x\n", __FUNCTION__, instr ); /*exit(0);*/}while(0);
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#define ptr_N cpu->ptr_N
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#define ptr_Z cpu->ptr_Z
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#define ptr_C cpu->ptr_C
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#define ptr_V cpu->ptr_V
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#define ptr_I cpu->ptr_I
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#define ptr_T cpu->ptr_T
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#define ptr_CPSR cpu->ptr_gpr[16]
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// For MUL instructions
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#define RDHi ((instr >> 16) & 0xF)
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#define RDLo ((instr >> 12) & 0xF)
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#define MUL_RD ((instr >> 16) & 0xF)
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#define MUL_RN ((instr >> 12) & 0xF)
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#define RS ((instr >> 8) & 0xF)
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#define RD ((instr >> 12) & 0xF)
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#define RN ((instr >> 16) & 0xF)
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#define RM (instr & 0xF)
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/* for MUL instructions */
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/*xxxx xxxx xxxx 1111 xxxx xxxx xxxx xxxx */
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#define RDHi ((instr >> 16) & 0xF)
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/*xxxx xxxx xxxx xxxx 1111 xxxx xxxx xxxx */
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#define RDLo ((instr >> 12) & 0xF)
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/*xxxx xxxx xxxx 1111 xxxx xxxx xxxx xxxx */
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#define MUL_RD ((instr >> 16) & 0xF)
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/*xxxx xxxx xxxx xxxx 1111 xxxx xxxx xxxx */
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#define MUL_RN ((instr >> 12) & 0xF)
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/*xxxx xxxx xxxx xxxx xxxx 1111 xxxx xxxx */
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#define RS ((instr >> 8) & 0xF)
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// CP15 registers
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#define OPCODE_1 BITS(21, 23)
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#define CRn BITS(16, 19)
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#define CRm BITS(0, 3)
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#define OPCODE_2 BITS(5, 7)
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/*xxxx xxxx xxxx xxxx 1111 xxxx xxxx xxxx */
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#define RD ((instr >> 12) & 0xF)
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/*xxxx xxxx xxxx 1111 xxxx xxxx xxxx xxxx */
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#define RN ((instr >> 16) & 0xF)
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/*xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 */
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#define RM (instr & 0xF)
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#define I BIT(25)
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#define S BIT(20)
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/* CP15 registers */
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#define OPCODE_1 BITS(21, 23)
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#define CRn BITS(16, 19)
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#define CRm BITS(0, 3)
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#define OPCODE_2 BITS(5, 7)
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#define SHIFT BITS(5,6)
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#define SHIFT_IMM BITS(7,11)
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#define IMMH BITS(8,11)
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#define IMML BITS(0,3)
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/*xxxx xx1x xxxx xxxx xxxx xxxx xxxx xxxx */
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#define I BIT(25)
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/*xxxx xxxx xxx1 xxxx xxxx xxxx xxxx xxxx */
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#define S BIT(20)
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#define LSPBIT BIT(24)
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#define LSUBIT BIT(23)
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#define LSBBIT BIT(22)
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#define LSWBIT BIT(21)
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#define LSLBIT BIT(20)
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#define LSSHBITS BITS(5,6)
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#define OFFSET12 BITS(0,11)
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#define SBIT BIT(20)
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#define DESTReg (BITS (12, 15))
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#define SHIFT BITS(5,6)
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#define SHIFT_IMM BITS(7,11)
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#define IMMH BITS(8,11)
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#define IMML BITS(0,3)
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#define LSPBIT BIT(24)
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#define LSUBIT BIT(23)
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#define LSBBIT BIT(22)
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#define LSWBIT BIT(21)
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#define LSLBIT BIT(20)
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#define LSSHBITS BITS(5,6)
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#define OFFSET12 BITS(0,11)
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#define SBIT BIT(20)
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#define DESTReg (BITS (12, 15))
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/* they are in unused state, give a corrent value when using */
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// They are in unused state, give a corrent value when using
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#define IS_V5E 0
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#define IS_V5 0
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#define IS_V6 0
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#define LHSReg 0
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/* temp define the using the pc reg need implement a flow */
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#define STORE_CHECK_RD_PC ADD(R(RD), CONST(INSTR_SIZE * 2))
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// Temp define the using the pc reg need implement a flow
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#define STORE_CHECK_RD_PC ADD(R(RD), CONST(INSTR_SIZE * 2))
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#define OPERAND operand(cpu,instr,bb,NULL)
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#define SCO_OPERAND(sco) operand(cpu,instr,bb,sco)
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#define BOPERAND boperand(instr)
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#define OPERAND operand(cpu,instr,bb,NULL)
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#define SCO_OPERAND(sco) operand(cpu,instr,bb,sco)
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#define BOPERAND boperand(instr)
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#define CHECK_RN_PC (RN==15? ADD(AND(R(RN), CONST(~0x1)), CONST(INSTR_SIZE * 2)):R(RN))
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#define CHECK_RN_PC_WA (RN==15? ADD(AND(R(RN), CONST(~0x3)), CONST(INSTR_SIZE * 2)):R(RN))
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#define CHECK_RN_PC (RN == 15 ? ADD(AND(R(RN), CONST(~0x1)), CONST(INSTR_SIZE * 2)) : R(RN))
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#define CHECK_RN_PC_WA (RN == 15 ? ADD(AND(R(RN), CONST(~0x3)), CONST(INSTR_SIZE * 2)) : R(RN))
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#define GET_USER_MODE() (OR(ICMP_EQ(R(MODE_REG), CONST(USER32MODE)), ICMP_EQ(R(MODE_REG), CONST(SYSTEM32MODE))))
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#define GET_USER_MODE() (OR(ICMP_EQ(R(MODE_REG), CONST(USER32MODE)), ICMP_EQ(R(MODE_REG), CONST(SYSTEM32MODE))))
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int decode_arm_instr(uint32_t instr, int32_t *idx);
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enum DECODE_STATUS {
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DECODE_SUCCESS,
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DECODE_FAILURE
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DECODE_SUCCESS,
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DECODE_FAILURE
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};
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struct instruction_set_encoding_item {
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const char *name;
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int attribute_value;
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int version;
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u32 content[21];
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const char *name;
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int attribute_value;
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int version;
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u32 content[21];
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};
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typedef struct instruction_set_encoding_item ISEITEM;
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#define RECORD_WB(value, flag) {cpu->dyncom_engine->wb_value = value;cpu->dyncom_engine->wb_flag = flag;}
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#define RECORD_WB(value, flag) { cpu->dyncom_engine->wb_value = value;cpu->dyncom_engine->wb_flag = flag; }
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#define INIT_WB(wb_value, wb_flag) RECORD_WB(wb_value, wb_flag)
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#define EXECUTE_WB(base_reg) {if(cpu->dyncom_engine->wb_flag) \
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LET(base_reg, cpu->dyncom_engine->wb_value);}
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inline int get_reg_count(uint32_t instr){
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int i = BITS(0,15);
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int count = 0;
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while(i){
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if(i & 1)
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count ++;
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i = i >> 1;
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}
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return count;
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#define EXECUTE_WB(base_reg) { if(cpu->dyncom_engine->wb_flag) LET(base_reg, cpu->dyncom_engine->wb_value); }
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inline int get_reg_count(uint32_t instr) {
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int i = BITS(0, 15);
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int count = 0;
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while (i) {
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if (i & 1)
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count++;
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i = i >> 1;
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}
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return count;
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}
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enum ARMVER {
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INVALID = 0,
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ARMALL,
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ARMV4,
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ARMV4T,
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ARMV5T,
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ARMV5TE,
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ARMV5TEJ,
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ARMV6,
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ARM1176JZF_S,
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ARMVFP2,
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ARMVFP3
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INVALID = 0,
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ARMALL,
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ARMV4,
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ARMV4T,
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ARMV5T,
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ARMV5TE,
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ARMV5TEJ,
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ARMV6,
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ARM1176JZF_S,
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ARMVFP2,
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ARMVFP3,
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ARMV6K,
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};
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//extern const INSTRACT arm_instruction_action[];
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extern const ISEITEM arm_instruction[];
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#endif
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@ -622,9 +622,7 @@ void LdnStM(DecrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int
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}
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unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
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unsigned int start_addr = rn - count * 4 + 4;
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unsigned int end_addr = rn;
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virt_addr = end_addr;
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virt_addr = start_addr;
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if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) {
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@ -1104,10 +1102,10 @@ typedef struct _blx_1_thumb {
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}blx_1_thumb;
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typedef struct _pkh_inst {
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u32 Rm;
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u32 Rn;
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u32 Rd;
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u8 imm;
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unsigned int Rm;
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unsigned int Rn;
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unsigned int Rd;
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unsigned char imm;
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} pkh_inst;
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typedef arm_inst * ARM_INST_PTR;
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@ -1740,40 +1738,31 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(unsigned int inst, int index)
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(ldrex)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
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ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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generic_arm_inst *inst_cream = (generic_arm_inst *)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->idx = index;
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inst_base->br = (BITS(inst, 12, 15) == 15) ? INDIRECT_BRANCH : NON_BRANCH; // Branch if dest is R15
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inst_cream->inst = inst;
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//inst_cream->get_addr = get_calc_addr_op(inst);
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inst_cream->Rn = BITS(inst, 16, 19);
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inst_cream->Rd = BITS(inst, 12, 15);
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if (BITS(inst, 12, 15) == 15) {
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inst_base->br = INDIRECT_BRANCH;
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}
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexb)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
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ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_cream->inst = inst;
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inst_cream->get_addr = get_calc_addr_op(inst);
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if (BITS(inst, 12, 15) == 15) {
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inst_base->br = INDIRECT_BRANCH;
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}
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return inst_base;
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return INTERPRETER_TRANSLATE(ldrex)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexh)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(ldrex)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexd)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(ldrex)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(ldrh)(unsigned int inst, int index)
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{
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@ -2623,37 +2612,30 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
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ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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generic_arm_inst *inst_cream = (generic_arm_inst *)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_cream->inst = inst;
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inst_cream->get_addr = get_calc_addr_op(inst);
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inst_cream->Rn = BITS(inst, 16, 19);
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inst_cream->Rd = BITS(inst, 12, 15);
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inst_cream->Rm = BITS(inst, 0, 3);
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if (BITS(inst, 12, 15) == 15) {
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inst_base->br = INDIRECT_BRANCH;
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}
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(strexb)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
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ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_cream->inst = inst;
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inst_cream->get_addr = get_calc_addr_op(inst);
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if (BITS(inst, 12, 15) == 15) {
|
||||
inst_base->br = INDIRECT_BRANCH;
|
||||
}
|
||||
return inst_base;
|
||||
return INTERPRETER_TRANSLATE(strex)(inst, index);
|
||||
}
|
||||
ARM_INST_PTR INTERPRETER_TRANSLATE(strexh)(unsigned int inst, int index)
|
||||
{
|
||||
return INTERPRETER_TRANSLATE(strex)(inst, index);
|
||||
}
|
||||
ARM_INST_PTR INTERPRETER_TRANSLATE(strexd)(unsigned int inst, int index)
|
||||
{
|
||||
return INTERPRETER_TRANSLATE(strex)(inst, index);
|
||||
}
|
||||
ARM_INST_PTR INTERPRETER_TRANSLATE(strh)(unsigned int inst, int index)
|
||||
{
|
||||
|
|
@ -3355,6 +3337,11 @@ const transop_fp_t arm_instruction_trans[] = {
|
|||
INTERPRETER_TRANSLATE(ldc),
|
||||
INTERPRETER_TRANSLATE(swi),
|
||||
INTERPRETER_TRANSLATE(bbl),
|
||||
INTERPRETER_TRANSLATE(ldrexd),
|
||||
INTERPRETER_TRANSLATE(strexd),
|
||||
INTERPRETER_TRANSLATE(ldrexh),
|
||||
INTERPRETER_TRANSLATE(strexh),
|
||||
|
||||
// All the thumb instructions should be placed the end of table
|
||||
INTERPRETER_TRANSLATE(b_2_thumb),
|
||||
INTERPRETER_TRANSLATE(b_cond_thumb),
|
||||
|
|
@ -3551,6 +3538,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
#define CRm inst_cream->crm
|
||||
#define CP15_REG(n) cpu->CP15[CP15(n)]
|
||||
#define RD cpu->Reg[inst_cream->Rd]
|
||||
#define RD2 cpu->Reg[inst_cream->Rd + 1]
|
||||
#define RN cpu->Reg[inst_cream->Rn]
|
||||
#define RM cpu->Reg[inst_cream->Rm]
|
||||
#define RS cpu->Reg[inst_cream->Rs]
|
||||
|
|
@ -3762,14 +3750,18 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
case 182: goto LDC_INST; \
|
||||
case 183: goto SWI_INST; \
|
||||
case 184: goto BBL_INST; \
|
||||
case 185: goto B_2_THUMB ; \
|
||||
case 186: goto B_COND_THUMB ; \
|
||||
case 187: goto BL_1_THUMB ; \
|
||||
case 188: goto BL_2_THUMB ; \
|
||||
case 189: goto BLX_1_THUMB ; \
|
||||
case 190: goto DISPATCH; \
|
||||
case 191: goto INIT_INST_LENGTH; \
|
||||
case 192: goto END; \
|
||||
case 185: goto LDREXD_INST; \
|
||||
case 186: goto STREXD_INST; \
|
||||
case 187: goto LDREXH_INST; \
|
||||
case 188: goto STREXH_INST; \
|
||||
case 189: goto B_2_THUMB ; \
|
||||
case 190: goto B_COND_THUMB ; \
|
||||
case 191: goto BL_1_THUMB ; \
|
||||
case 192: goto BL_2_THUMB ; \
|
||||
case 193: goto BLX_1_THUMB ; \
|
||||
case 194: goto DISPATCH; \
|
||||
case 195: goto INIT_INST_LENGTH; \
|
||||
case 196: goto END; \
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -3830,8 +3822,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
&&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST,
|
||||
&&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST,
|
||||
&&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,&&MSR_INST,
|
||||
&&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST,&&SWI_INST,&&BBL_INST,&&B_2_THUMB, &&B_COND_THUMB,
|
||||
&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH,&&INIT_INST_LENGTH,&&END
|
||||
&&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST,&&SWI_INST,&&BBL_INST,&&LDREXD_INST,
|
||||
&&STREXD_INST,&&LDREXH_INST,&&STREXH_INST,&&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH,
|
||||
&&INIT_INST_LENGTH,&&END
|
||||
};
|
||||
#endif
|
||||
arm_inst * inst_base;
|
||||
|
|
@ -4432,45 +4425,84 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
|
||||
LDREX_INST:
|
||||
{
|
||||
ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
|
||||
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)];
|
||||
unsigned int read_addr = RN;
|
||||
|
||||
unsigned int value = Memory::Read32(addr);
|
||||
|
||||
add_exclusive_addr(cpu, addr);
|
||||
add_exclusive_addr(cpu, read_addr);
|
||||
cpu->exclusive_state = 1;
|
||||
|
||||
cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
|
||||
if (BITS(inst_cream->inst, 12, 15) == 15) {
|
||||
INC_PC(sizeof(ldst_inst));
|
||||
RD = Memory::Read32(read_addr);
|
||||
if (inst_cream->Rd == 15) {
|
||||
INC_PC(sizeof(generic_arm_inst));
|
||||
goto DISPATCH;
|
||||
}
|
||||
}
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
INC_PC(sizeof(ldst_inst));
|
||||
INC_PC(sizeof(generic_arm_inst));
|
||||
FETCH_INST;
|
||||
GOTO_NEXT_INST;
|
||||
}
|
||||
LDREXB_INST:
|
||||
{
|
||||
ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
|
||||
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)];
|
||||
unsigned int read_addr = RN;
|
||||
|
||||
unsigned int value = Memory::Read8(addr);
|
||||
|
||||
add_exclusive_addr(cpu, addr);
|
||||
add_exclusive_addr(cpu, read_addr);
|
||||
cpu->exclusive_state = 1;
|
||||
|
||||
cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
|
||||
if (BITS(inst_cream->inst, 12, 15) == 15) {
|
||||
INC_PC(sizeof(ldst_inst));
|
||||
RD = Memory::Read8(read_addr);
|
||||
if (inst_cream->Rd == 15) {
|
||||
INC_PC(sizeof(generic_arm_inst));
|
||||
goto DISPATCH;
|
||||
}
|
||||
}
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
INC_PC(sizeof(ldst_inst));
|
||||
INC_PC(sizeof(generic_arm_inst));
|
||||
FETCH_INST;
|
||||
GOTO_NEXT_INST;
|
||||
}
|
||||
LDREXH_INST:
|
||||
{
|
||||
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
unsigned int read_addr = RN;
|
||||
|
||||
add_exclusive_addr(cpu, read_addr);
|
||||
cpu->exclusive_state = 1;
|
||||
|
||||
RD = Memory::Read16(read_addr);
|
||||
if (inst_cream->Rd == 15) {
|
||||
INC_PC(sizeof(generic_arm_inst));
|
||||
goto DISPATCH;
|
||||
}
|
||||
}
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
INC_PC(sizeof(generic_arm_inst));
|
||||
FETCH_INST;
|
||||
GOTO_NEXT_INST;
|
||||
}
|
||||
LDREXD_INST:
|
||||
{
|
||||
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
unsigned int read_addr = RN;
|
||||
|
||||
add_exclusive_addr(cpu, read_addr);
|
||||
cpu->exclusive_state = 1;
|
||||
// TODO(bunnei): Do we need to also make [read_addr + 4] exclusive?
|
||||
|
||||
RD = Memory::Read32(read_addr);
|
||||
RD2 = Memory::Read32(read_addr + 4);
|
||||
|
||||
if (inst_cream->Rd == 15) {
|
||||
INC_PC(sizeof(generic_arm_inst));
|
||||
goto DISPATCH;
|
||||
}
|
||||
}
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
INC_PC(sizeof(generic_arm_inst));
|
||||
FETCH_INST;
|
||||
GOTO_NEXT_INST;
|
||||
}
|
||||
|
|
@ -5762,46 +5794,96 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
STREX_INST:
|
||||
{
|
||||
ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)];
|
||||
unsigned int value = cpu->Reg[BITS(inst_cream->inst, 0, 3)];
|
||||
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
|
||||
|
||||
int dest_reg = BITS(inst_cream->inst, 12, 15);
|
||||
if((exclusive_detect(cpu, addr) == 0) && (cpu->exclusive_state == 1)){
|
||||
remove_exclusive(cpu, addr);
|
||||
cpu->Reg[dest_reg] = 0;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
unsigned int write_addr = cpu->Reg[inst_cream->Rn];
|
||||
|
||||
if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
|
||||
remove_exclusive(cpu, write_addr);
|
||||
cpu->exclusive_state = 0;
|
||||
|
||||
Memory::Write32(addr, value);
|
||||
Memory::Write32(write_addr, cpu->Reg[inst_cream->Rm]);
|
||||
RD = 0;
|
||||
} else {
|
||||
// Failed to write due to mutex access
|
||||
cpu->Reg[dest_reg] = 1;
|
||||
RD = 1;
|
||||
}
|
||||
}
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
INC_PC(sizeof(ldst_inst));
|
||||
INC_PC(sizeof(generic_arm_inst));
|
||||
FETCH_INST;
|
||||
GOTO_NEXT_INST;
|
||||
}
|
||||
STREXB_INST:
|
||||
{
|
||||
ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
|
||||
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
|
||||
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)];
|
||||
unsigned int value = cpu->Reg[BITS(inst_cream->inst, 0, 3)] & 0xff;
|
||||
int dest_reg = BITS(inst_cream->inst, 12, 15);
|
||||
if((exclusive_detect(cpu, addr) == 0) && (cpu->exclusive_state == 1)){
|
||||
remove_exclusive(cpu, addr);
|
||||
cpu->Reg[dest_reg] = 0;
|
||||
unsigned int write_addr = cpu->Reg[inst_cream->Rn];
|
||||
|
||||
if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
|
||||
remove_exclusive(cpu, write_addr);
|
||||
cpu->exclusive_state = 0;
|
||||
Memory::Write8(addr, value);
|
||||
|
||||
Memory::Write8(write_addr, cpu->Reg[inst_cream->Rm]);
|
||||
RD = 0;
|
||||
} else {
|
||||
cpu->Reg[dest_reg] = 1;
|
||||
// Failed to write due to mutex access
|
||||
RD = 1;
|
||||
}
|
||||
}
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
INC_PC(sizeof(ldst_inst));
|
||||
INC_PC(sizeof(generic_arm_inst));
|
||||
FETCH_INST;
|
||||
GOTO_NEXT_INST;
|
||||
}
|
||||
STREXD_INST:
|
||||
{
|
||||
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
|
||||
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
unsigned int write_addr = cpu->Reg[inst_cream->Rn];
|
||||
|
||||
if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
|
||||
remove_exclusive(cpu, write_addr);
|
||||
cpu->exclusive_state = 0;
|
||||
// TODO(bunnei): Remove exclusive from [write_addr + 4] if we implement this in LDREXD
|
||||
|
||||
Memory::Write32(write_addr, cpu->Reg[inst_cream->Rm]);
|
||||
Memory::Write32(write_addr + 4, cpu->Reg[inst_cream->Rm + 1]);
|
||||
RD = 0;
|
||||
}
|
||||
else {
|
||||
// Failed to write due to mutex access
|
||||
RD = 1;
|
||||
}
|
||||
}
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
INC_PC(sizeof(generic_arm_inst));
|
||||
FETCH_INST;
|
||||
GOTO_NEXT_INST;
|
||||
}
|
||||
STREXH_INST:
|
||||
{
|
||||
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
|
||||
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
unsigned int write_addr = cpu->Reg[inst_cream->Rn];
|
||||
|
||||
if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
|
||||
remove_exclusive(cpu, write_addr);
|
||||
cpu->exclusive_state = 0;
|
||||
|
||||
Memory::Write16(write_addr, cpu->Reg[inst_cream->Rm]);
|
||||
RD = 0;
|
||||
} else {
|
||||
// Failed to write due to mutex access
|
||||
RD = 1;
|
||||
}
|
||||
}
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
INC_PC(sizeof(generic_arm_inst));
|
||||
FETCH_INST;
|
||||
GOTO_NEXT_INST;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue