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ARM: Merge latest VFP fixes from 3dmoo team.
This commit is contained in:
bunnei
parent
2ca12e7f38
commit
bc6989b075
4 changed files with 2161 additions and 1869 deletions
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@ -28,6 +28,8 @@
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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#define DEBUG DBG
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//ARMul_State* persistent_state; /* function calls from SoftFloat lib don't have an access to ARMul_state. */
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unsigned
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@ -41,11 +43,11 @@ VFPInit (ARMul_State *state)
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//persistent_state = state;
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/* Reset only specify VFP_FPEXC_EN = '0' */
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return No_exp;
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return 0;
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}
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unsigned
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VFPMRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value)
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VFPMRC (ARMul_State * state, unsigned type, u32 instr, u32 * value)
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{
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/* MRC<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>} */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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@ -59,20 +61,19 @@ VFPMRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value)
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/* CRn/opc1 CRm/opc2 */
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if (CoProc == 10 || CoProc == 11)
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{
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if (CoProc == 10 || CoProc == 11) {
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#define VFP_MRC_TRANS
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_MRC_TRANS
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}
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DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
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DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
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instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2);
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return ARMul_CANT;
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}
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unsigned
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VFPMCR (ARMul_State * state, unsigned type, ARMword instr, ARMword value)
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VFPMCR (ARMul_State * state, unsigned type, u32 instr, u32 value)
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{
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/* MCR<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>} */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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@ -85,20 +86,19 @@ VFPMCR (ARMul_State * state, unsigned type, ARMword instr, ARMword value)
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/* TODO check access permission */
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/* CRn/opc1 CRm/opc2 */
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if (CoProc == 10 || CoProc == 11)
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{
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if (CoProc == 10 || CoProc == 11) {
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#define VFP_MCR_TRANS
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_MCR_TRANS
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}
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DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
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DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
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instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2);
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return ARMul_CANT;
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}
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unsigned
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VFPMRRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value1, ARMword * value2)
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VFPMRRC (ARMul_State * state, unsigned type, u32 instr, u32 * value1, u32 * value2)
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{
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/* MCRR<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm> */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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@ -107,20 +107,19 @@ VFPMRRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value1, AR
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int Rt2 = BITS (16, 19);
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int CRm = BITS (0, 3);
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if (CoProc == 10 || CoProc == 11)
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{
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if (CoProc == 10 || CoProc == 11) {
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#define VFP_MRRC_TRANS
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_MRRC_TRANS
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}
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DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
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DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
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instr, CoProc, OPC_1, Rt, Rt2, CRm);
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return ARMul_CANT;
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}
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unsigned
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VFPMCRR (ARMul_State * state, unsigned type, ARMword instr, ARMword value1, ARMword value2)
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VFPMCRR (ARMul_State * state, unsigned type, u32 instr, u32 value1, u32 value2)
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{
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/* MCRR<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm> */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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@ -133,20 +132,19 @@ VFPMCRR (ARMul_State * state, unsigned type, ARMword instr, ARMword value1, ARMw
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/* CRn/opc1 CRm/opc2 */
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if (CoProc == 11 || CoProc == 10)
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{
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if (CoProc == 11 || CoProc == 10) {
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#define VFP_MCRR_TRANS
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_MCRR_TRANS
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}
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DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
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DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
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instr, CoProc, OPC_1, Rt, Rt2, CRm);
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return ARMul_CANT;
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}
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unsigned
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VFPSTC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value)
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VFPSTC (ARMul_State * state, unsigned type, u32 instr, u32 * value)
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{
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/* STC{L}<c> <coproc>,<CRd>,[<Rn>],<option> */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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@ -161,20 +159,19 @@ VFPSTC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value)
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/* TODO check access permission */
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/* VSTM */
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if ( (P|U|D|W) == 0 )
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{
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DEBUG_LOG(ARM11, "In %s, UNDEFINED\n", __FUNCTION__); exit(-1);
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if ( (P|U|D|W) == 0 ) {
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DEBUG("In %s, UNDEFINED\n", __FUNCTION__);
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exit(-1);
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}
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if (CoProc == 10 || CoProc == 11)
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{
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if (CoProc == 10 || CoProc == 11) {
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#if 1
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if (P == 0 && U == 0 && W == 0)
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{
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DEBUG_LOG(ARM11, "VSTM Related encodings\n"); exit(-1);
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if (P == 0 && U == 0 && W == 0) {
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DEBUG("VSTM Related encodings\n");
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exit(-1);
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}
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if (P == U && W == 1)
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{
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DEBUG_LOG(ARM11, "UNDEFINED\n"); exit(-1);
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if (P == U && W == 1) {
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DEBUG("UNDEFINED\n");
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exit(-1);
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}
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#endif
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@ -182,14 +179,14 @@ VFPSTC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value)
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_STC_TRANS
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}
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DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
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DEBUG("Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
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instr, CoProc, CRd, Rn, imm8, P, U, D, W);
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return ARMul_CANT;
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}
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unsigned
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VFPLDC (ARMul_State * state, unsigned type, ARMword instr, ARMword value)
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VFPLDC (ARMul_State * state, unsigned type, u32 instr, u32 value)
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{
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/* LDC{L}<c> <coproc>,<CRd>,[<Rn>] */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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@ -203,24 +200,23 @@ VFPLDC (ARMul_State * state, unsigned type, ARMword instr, ARMword value)
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/* TODO check access permission */
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if ( (P|U|D|W) == 0 )
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{
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DEBUG_LOG(ARM11, "In %s, UNDEFINED\n", __FUNCTION__); exit(-1);
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if ( (P|U|D|W) == 0 ) {
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DEBUG("In %s, UNDEFINED\n", __FUNCTION__);
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exit(-1);
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}
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if (CoProc == 10 || CoProc == 11)
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{
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if (CoProc == 10 || CoProc == 11) {
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#define VFP_LDC_TRANS
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_LDC_TRANS
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}
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DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
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DEBUG("Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
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instr, CoProc, CRd, Rn, imm8, P, U, D, W);
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return ARMul_CANT;
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}
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unsigned
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VFPCDP (ARMul_State * state, unsigned type, ARMword instr)
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VFPCDP (ARMul_State * state, unsigned type, u32 instr)
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{
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/* CDP<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2> */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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@ -230,12 +226,56 @@ VFPCDP (ARMul_State * state, unsigned type, ARMword instr)
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int CRm = BITS (0, 3);
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int OPC_2 = BITS (5, 7);
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//ichfly
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/*if ((instr & 0x0FBF0FD0) == 0x0EB70AC0) //vcvt.f64.f32 d8, s16 (s is bit 0-3 and LSB bit 22) (d is bit 12 - 15 MSB is Bit 6)
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{
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struct vfp_double vdd;
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struct vfp_single vsd;
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int dn = BITS(12, 15) + (BIT(22) << 4);
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int sd = (BITS(0, 3) << 1) + BIT(5);
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s32 n = vfp_get_float(state, sd);
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vfp_single_unpack(&vsd, n);
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if (vsd.exponent & 0x80)
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{
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vdd.exponent = (vsd.exponent&~0x80) | 0x400;
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}
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else
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{
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vdd.exponent = vsd.exponent | 0x380;
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}
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vdd.sign = vsd.sign;
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vdd.significand = (u64)(vsd.significand & ~0xC0000000) << 32; // I have no idea why but the 2 uppern bits are not from the significand
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vfp_put_double(state, vfp_double_pack(&vdd), dn);
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return ARMul_DONE;
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}
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if ((instr & 0x0FBF0FD0) == 0x0EB70BC0) //vcvt.f32.f64 s15, d6
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{
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struct vfp_double vdd;
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struct vfp_single vsd;
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int sd = BITS(0, 3) + (BIT(5) << 4);
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int dn = (BITS(12, 15) << 1) + BIT(22);
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vfp_double_unpack(&vdd, vfp_get_double(state, sd));
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if (vdd.exponent & 0x400) //todo if the exponent is to low or to high for this convert
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{
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vsd.exponent = (vdd.exponent) | 0x80;
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}
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else
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{
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vsd.exponent = vdd.exponent & ~0x80;
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}
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vsd.exponent &= 0xFF;
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// vsd.exponent = vdd.exponent >> 3;
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vsd.sign = vdd.sign;
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vsd.significand = ((u64)(vdd.significand ) >> 32)& ~0xC0000000;
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vfp_put_float(state, vfp_single_pack(&vsd), dn);
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return ARMul_DONE;
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}*/
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/* TODO check access permission */
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/* CRn/opc1 CRm/opc2 */
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if (CoProc == 10 || CoProc == 11)
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{
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if (CoProc == 10 || CoProc == 11) {
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#define VFP_CDP_TRANS
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_CDP_TRANS
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@ -250,7 +290,7 @@ VFPCDP (ARMul_State * state, unsigned type, ARMword instr)
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return ARMul_DONE;
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}
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DEBUG_LOG(ARM11, "Can't identify %x\n", instr);
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DEBUG("Can't identify %x\n", instr);
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return ARMul_CANT;
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}
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@ -301,13 +341,13 @@ VFPCDP (ARMul_State * state, unsigned type, ARMword instr)
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/* Miscellaneous functions */
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int32_t vfp_get_float(arm_core_t* state, unsigned int reg)
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{
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DBG("VFP get float: s%d=[%08x]\n", reg, state->ExtReg[reg]);
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DEBUG("VFP get float: s%d=[%08x]\n", reg, state->ExtReg[reg]);
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return state->ExtReg[reg];
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}
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void vfp_put_float(arm_core_t* state, int32_t val, unsigned int reg)
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{
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DBG("VFP put float: s%d <= [%08x]\n", reg, val);
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DEBUG("VFP put float: s%d <= [%08x]\n", reg, val);
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state->ExtReg[reg] = val;
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}
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@ -315,13 +355,13 @@ uint64_t vfp_get_double(arm_core_t* state, unsigned int reg)
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{
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uint64_t result;
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result = ((uint64_t) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2];
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DBG("VFP get double: s[%d-%d]=[%016llx]\n", reg*2+1, reg*2, result);
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DEBUG("VFP get double: s[%d-%d]=[%016llx]\n", reg*2+1, reg*2, result);
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return result;
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}
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void vfp_put_double(arm_core_t* state, uint64_t val, unsigned int reg)
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{
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DBG("VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg*2+1, reg*2, (uint32_t) (val>>32), (uint32_t) (val & 0xffffffff));
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DEBUG("VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg*2+1, reg*2, (uint32_t) (val>>32), (uint32_t) (val & 0xffffffff));
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state->ExtReg[reg*2] = (uint32_t) (val & 0xffffffff);
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state->ExtReg[reg*2+1] = (uint32_t) (val>>32);
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}
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@ -338,7 +378,7 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc
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vfpdebug("VFP: raising exceptions %08x\n", exceptions);
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if (exceptions == VFP_EXCEPTION_ERROR) {
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DEBUG_LOG(ARM11, "unhandled bounce %x\n", inst);
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DEBUG("unhandled bounce %x\n", inst);
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exit(-1);
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return;
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}
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@ -44,7 +44,7 @@
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#define pr_info //printf
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#define pr_debug //printf
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static u32 vfp_fls(int x);
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static u32 fls(int x);
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#define do_div(n, base) {n/=base;}
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/* From vfpinstr.h */
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@ -502,7 +502,7 @@ struct op {
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u32 flags;
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};
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static u32 vfp_fls(int x)
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static u32 fls(int x)
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{
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int r = 32;
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@ -532,4 +532,9 @@ static u32 vfp_fls(int x)
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}
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u32 vfp_double_normaliseroundintern(ARMul_State* state, struct vfp_double *vd, u32 fpscr, u32 exceptions, const char *func);
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u32 vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn, struct vfp_double *vdm, u32 fpscr);
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u32 vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn, struct vfp_double *vdm, u32 fpscr);
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u32 vfp_double_fcvtsinterncutting(ARMul_State* state, int sd, struct vfp_double* dm, u32 fpscr);
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#endif
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@ -56,9 +56,9 @@
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#include "core/arm/skyeye_common/vfp/asm_vfp.h"
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static struct vfp_double vfp_double_default_qnan = {
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//.exponent = 2047,
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//.sign = 0,
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//.significand = VFP_DOUBLE_SIGNIFICAND_QNAN,
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2047,
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0,
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VFP_DOUBLE_SIGNIFICAND_QNAN,
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};
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static void vfp_double_dump(const char *str, struct vfp_double *d)
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@ -69,9 +69,9 @@ static void vfp_double_dump(const char *str, struct vfp_double *d)
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static void vfp_double_normalise_denormal(struct vfp_double *vd)
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{
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int bits = 31 - vfp_fls(vd->significand >> 32);
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int bits = 31 - fls((ARMword)(vd->significand >> 32));
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if (bits == 31)
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bits = 63 - vfp_fls(vd->significand);
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bits = 63 - fls((ARMword)vd->significand);
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vfp_double_dump("normalise_denormal: in", vd);
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@ -83,6 +83,134 @@ static void vfp_double_normalise_denormal(struct vfp_double *vd)
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vfp_double_dump("normalise_denormal: out", vd);
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}
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u32 vfp_double_normaliseroundintern(ARMul_State* state, struct vfp_double *vd, u32 fpscr, u32 exceptions, const char *func)
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{
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u64 significand, incr;
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int exponent, shift, underflow;
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u32 rmode;
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vfp_double_dump("pack: in", vd);
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/*
|
||||
* Infinities and NaNs are a special case.
|
||||
*/
|
||||
if (vd->exponent == 2047 && (vd->significand == 0 || exceptions))
|
||||
goto pack;
|
||||
|
||||
/*
|
||||
* Special-case zero.
|
||||
*/
|
||||
if (vd->significand == 0) {
|
||||
vd->exponent = 0;
|
||||
goto pack;
|
||||
}
|
||||
|
||||
exponent = vd->exponent;
|
||||
significand = vd->significand;
|
||||
|
||||
shift = 32 - fls((ARMword)(significand >> 32));
|
||||
if (shift == 32)
|
||||
shift = 64 - fls((ARMword)significand);
|
||||
if (shift) {
|
||||
exponent -= shift;
|
||||
significand <<= shift;
|
||||
}
|
||||
|
||||
#if 1
|
||||
vd->exponent = exponent;
|
||||
vd->significand = significand;
|
||||
vfp_double_dump("pack: normalised", vd);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Tiny number?
|
||||
*/
|
||||
underflow = exponent < 0;
|
||||
if (underflow) {
|
||||
significand = vfp_shiftright64jamming(significand, -exponent);
|
||||
exponent = 0;
|
||||
#if 1
|
||||
vd->exponent = exponent;
|
||||
vd->significand = significand;
|
||||
vfp_double_dump("pack: tiny number", vd);
|
||||
#endif
|
||||
if (!(significand & ((1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1)))
|
||||
underflow = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Select rounding increment.
|
||||
*/
|
||||
incr = 0;
|
||||
rmode = fpscr & FPSCR_RMODE_MASK;
|
||||
|
||||
if (rmode == FPSCR_ROUND_NEAREST) {
|
||||
incr = 1ULL << VFP_DOUBLE_LOW_BITS;
|
||||
if ((significand & (1ULL << (VFP_DOUBLE_LOW_BITS + 1))) == 0)
|
||||
incr -= 1;
|
||||
}
|
||||
else if (rmode == FPSCR_ROUND_TOZERO) {
|
||||
incr = 0;
|
||||
}
|
||||
else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0))
|
||||
incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1;
|
||||
|
||||
pr_debug("VFP: rounding increment = 0x%08llx\n", incr);
|
||||
|
||||
/*
|
||||
* Is our rounding going to overflow?
|
||||
*/
|
||||
if ((significand + incr) < significand) {
|
||||
exponent += 1;
|
||||
significand = (significand >> 1) | (significand & 1);
|
||||
incr >>= 1;
|
||||
#if 1
|
||||
vd->exponent = exponent;
|
||||
vd->significand = significand;
|
||||
vfp_double_dump("pack: overflow", vd);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* If any of the low bits (which will be shifted out of the
|
||||
* number) are non-zero, the result is inexact.
|
||||
*/
|
||||
if (significand & ((1 << (VFP_DOUBLE_LOW_BITS + 1)) - 1))
|
||||
exceptions |= FPSCR_IXC;
|
||||
|
||||
/*
|
||||
* Do our rounding.
|
||||
*/
|
||||
significand += incr;
|
||||
|
||||
/*
|
||||
* Infinity?
|
||||
*/
|
||||
if (exponent >= 2046) {
|
||||
exceptions |= FPSCR_OFC | FPSCR_IXC;
|
||||
if (incr == 0) {
|
||||
vd->exponent = 2045;
|
||||
vd->significand = 0x7fffffffffffffffULL;
|
||||
}
|
||||
else {
|
||||
vd->exponent = 2047; /* infinity */
|
||||
vd->significand = 0;
|
||||
}
|
||||
}
|
||||
else {
|
||||
if (significand >> (VFP_DOUBLE_LOW_BITS + 1) == 0)
|
||||
exponent = 0;
|
||||
if (exponent || significand > 0x8000000000000000ULL)
|
||||
underflow = 0;
|
||||
if (underflow)
|
||||
exceptions |= FPSCR_UFC;
|
||||
vd->exponent = exponent;
|
||||
vd->significand = significand >> 1;
|
||||
}
|
||||
pack:
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double *vd, u32 fpscr, u32 exceptions, const char *func)
|
||||
{
|
||||
u64 significand, incr;
|
||||
|
|
@ -108,9 +236,9 @@ u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double *vd,
|
|||
exponent = vd->exponent;
|
||||
significand = vd->significand;
|
||||
|
||||
shift = 32 - vfp_fls(significand >> 32);
|
||||
shift = 32 - fls((ARMword)(significand >> 32));
|
||||
if (shift == 32)
|
||||
shift = 64 - vfp_fls(significand);
|
||||
shift = 64 - fls((ARMword)significand);
|
||||
if (shift) {
|
||||
exponent -= shift;
|
||||
significand <<= shift;
|
||||
|
|
@ -287,7 +415,7 @@ static u32 vfp_double_fneg(ARMul_State* state, int dd, int unused, int dm, u32 f
|
|||
static u32 vfp_double_fsqrt(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
|
||||
{
|
||||
pr_debug("In %s\n", __FUNCTION__);
|
||||
struct vfp_double vdm, vdd, *vdp;
|
||||
vfp_double vdm, vdd, *vdp;
|
||||
int ret, tm;
|
||||
|
||||
vfp_double_unpack(&vdm, vfp_get_double(state, dm));
|
||||
|
|
@ -464,6 +592,49 @@ static u32 vfp_double_fcmpez(ARMul_State* state, int dd, int unused, int dm, u32
|
|||
return vfp_compare(state, dd, 1, VFP_REG_ZERO, fpscr);
|
||||
}
|
||||
|
||||
u32 vfp_double_fcvtsinterncutting(ARMul_State* state, int sd, struct vfp_double* dm, u32 fpscr) //ichfly for internal use only
|
||||
{
|
||||
struct vfp_single vsd;
|
||||
int tm;
|
||||
u32 exceptions = 0;
|
||||
|
||||
pr_debug("In %s\n", __FUNCTION__);
|
||||
|
||||
tm = vfp_double_type(dm);
|
||||
|
||||
/*
|
||||
* If we have a signalling NaN, signal invalid operation.
|
||||
*/
|
||||
if (tm == VFP_SNAN)
|
||||
exceptions = FPSCR_IOC;
|
||||
|
||||
if (tm & VFP_DENORMAL)
|
||||
vfp_double_normalise_denormal(dm);
|
||||
|
||||
vsd.sign = dm->sign;
|
||||
vsd.significand = vfp_hi64to32jamming(dm->significand);
|
||||
|
||||
/*
|
||||
* If we have an infinity or a NaN, the exponent must be 255
|
||||
*/
|
||||
if (tm & (VFP_INFINITY | VFP_NAN)) {
|
||||
vsd.exponent = 255;
|
||||
if (tm == VFP_QNAN)
|
||||
vsd.significand |= VFP_SINGLE_SIGNIFICAND_QNAN;
|
||||
goto pack_nan;
|
||||
}
|
||||
else if (tm & VFP_ZERO)
|
||||
vsd.exponent = 0;
|
||||
else
|
||||
vsd.exponent = dm->exponent - (1023 - 127);
|
||||
|
||||
return vfp_single_normaliseround(state, sd, &vsd, fpscr, exceptions, "fcvts");
|
||||
|
||||
pack_nan:
|
||||
vfp_put_float(state, vfp_single_pack(&vsd), sd);
|
||||
return exceptions;
|
||||
}
|
||||
|
||||
static u32 vfp_double_fcvts(ARMul_State* state, int sd, int unused, int dm, u32 fpscr)
|
||||
{
|
||||
struct vfp_double vdm;
|
||||
|
|
@ -564,7 +735,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
|
|||
/*
|
||||
* 2^0 <= m < 2^32-2^8
|
||||
*/
|
||||
d = (vdm.significand << 1) >> shift;
|
||||
d = (ARMword)((vdm.significand << 1) >> shift);
|
||||
rem = vdm.significand << (65 - shift);
|
||||
|
||||
if (rmode == FPSCR_ROUND_NEAREST) {
|
||||
|
|
@ -645,7 +816,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
|
|||
int shift = 1023 + 63 - vdm.exponent; /* 58 */
|
||||
u64 rem, incr = 0;
|
||||
|
||||
d = (vdm.significand << 1) >> shift;
|
||||
d = (ARMword)((vdm.significand << 1) >> shift);
|
||||
rem = vdm.significand << (65 - shift);
|
||||
|
||||
if (rmode == FPSCR_ROUND_NEAREST) {
|
||||
|
|
@ -660,8 +831,8 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
|
|||
|
||||
if ((rem + incr) < rem && d < 0xffffffff)
|
||||
d += 1;
|
||||
if (d > 0x7fffffff + (vdm.sign != 0)) {
|
||||
d = 0x7fffffff + (vdm.sign != 0);
|
||||
if (d > (0x7fffffff + (vdm.sign != 0))) {
|
||||
d = (0x7fffffff + (vdm.sign != 0));
|
||||
exceptions |= FPSCR_IOC;
|
||||
} else if (rem)
|
||||
exceptions |= FPSCR_IXC;
|
||||
|
|
@ -768,16 +939,14 @@ vfp_double_fadd_nonnumber(struct vfp_double *vdd, struct vfp_double *vdn,
|
|||
return exceptions;
|
||||
}
|
||||
|
||||
static u32
|
||||
vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn,
|
||||
struct vfp_double *vdm, u32 fpscr)
|
||||
u32 vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn,struct vfp_double *vdm, u32 fpscr)
|
||||
{
|
||||
u32 exp_diff;
|
||||
u64 m_sig;
|
||||
|
||||
if (vdn->significand & (1ULL << 63) ||
|
||||
vdm->significand & (1ULL << 63)) {
|
||||
pr_info("VFP: bad FP values\n");
|
||||
pr_info("VFP: bad FP values in %s\n", __func__);
|
||||
vfp_double_dump("VDN", vdn);
|
||||
vfp_double_dump("VDM", vdm);
|
||||
}
|
||||
|
|
@ -833,7 +1002,7 @@ vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static u32
|
||||
u32
|
||||
vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn,
|
||||
struct vfp_double *vdm, u32 fpscr)
|
||||
{
|
||||
|
|
@ -895,7 +1064,7 @@ vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn,
|
|||
#define NEG_SUBTRACT (1 << 1)
|
||||
|
||||
static u32
|
||||
vfp_double_multiply_accumulate(ARMul_State* state, int dd, int dn, int dm, u32 fpscr, u32 negate, const char *func)
|
||||
vfp_double_multiply_accumulate(ARMul_State* state, int dd, int dn, int dm, u32 fpscr, u32 negate, char *func)
|
||||
{
|
||||
struct vfp_double vdd, vdp, vdn, vdm;
|
||||
u32 exceptions;
|
||||
|
|
|
|||
|
|
@ -56,9 +56,9 @@
|
|||
#include "core/arm/skyeye_common/vfp/vfp.h"
|
||||
|
||||
static struct vfp_single vfp_single_default_qnan = {
|
||||
//.exponent = 255,
|
||||
//.sign = 0,
|
||||
//.significand = VFP_SINGLE_SIGNIFICAND_QNAN,
|
||||
255,
|
||||
0,
|
||||
VFP_SINGLE_SIGNIFICAND_QNAN,
|
||||
};
|
||||
|
||||
static void vfp_single_dump(const char *str, struct vfp_single *s)
|
||||
|
|
@ -69,7 +69,7 @@ static void vfp_single_dump(const char *str, struct vfp_single *s)
|
|||
|
||||
static void vfp_single_normalise_denormal(struct vfp_single *vs)
|
||||
{
|
||||
int bits = 31 - vfp_fls(vs->significand);
|
||||
int bits = 31 - fls(vs->significand);
|
||||
|
||||
vfp_single_dump("normalise_denormal: in", vs);
|
||||
|
||||
|
|
@ -111,7 +111,7 @@ u32 vfp_single_normaliseround(ARMul_State* state, int sd, struct vfp_single *vs,
|
|||
* bit 31, so we have VFP_SINGLE_LOW_BITS + 1 below the least
|
||||
* significant bit.
|
||||
*/
|
||||
shift = 32 - vfp_fls(significand);
|
||||
shift = 32 - fls(significand);
|
||||
if (shift < 32 && shift) {
|
||||
exponent -= shift;
|
||||
significand <<= shift;
|
||||
|
|
@ -321,7 +321,7 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand)
|
|||
{
|
||||
u64 v = (u64)a << 31;
|
||||
do_div(v, z);
|
||||
return v + (z >> 1);
|
||||
return (u32)(v + (z >> 1));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -491,6 +491,47 @@ static u32 vfp_single_fcmpez(ARMul_State* state, int sd, int unused, s32 m, u32
|
|||
return vfp_compare(state, sd, 1, 0, fpscr);
|
||||
}
|
||||
|
||||
static s64 vfp_single_to_doubleintern(ARMul_State* state, s32 m, u32 fpscr) //ichfly for internal use only
|
||||
{
|
||||
struct vfp_single vsm;
|
||||
struct vfp_double vdd;
|
||||
int tm;
|
||||
u32 exceptions = 0;
|
||||
|
||||
vfp_single_unpack(&vsm, m);
|
||||
|
||||
tm = vfp_single_type(&vsm);
|
||||
|
||||
/*
|
||||
* If we have a signalling NaN, signal invalid operation.
|
||||
*/
|
||||
if (tm == VFP_SNAN)
|
||||
exceptions = FPSCR_IOC;
|
||||
|
||||
if (tm & VFP_DENORMAL)
|
||||
vfp_single_normalise_denormal(&vsm);
|
||||
|
||||
vdd.sign = vsm.sign;
|
||||
vdd.significand = (u64)vsm.significand << 32;
|
||||
|
||||
/*
|
||||
* If we have an infinity or NaN, the exponent must be 2047.
|
||||
*/
|
||||
if (tm & (VFP_INFINITY | VFP_NAN)) {
|
||||
vdd.exponent = 2047;
|
||||
if (tm == VFP_QNAN)
|
||||
vdd.significand |= VFP_DOUBLE_SIGNIFICAND_QNAN;
|
||||
goto pack_nan;
|
||||
}
|
||||
else if (tm & VFP_ZERO)
|
||||
vdd.exponent = 0;
|
||||
else
|
||||
vdd.exponent = vsm.exponent + (1023 - 127);
|
||||
pack_nan:
|
||||
vfp_double_normaliseroundintern(state, &vdd, fpscr, exceptions, "fcvtd");
|
||||
return vfp_double_pack(&vdd);
|
||||
}
|
||||
|
||||
static u32 vfp_single_fcvtd(ARMul_State* state, int dd, int unused, s32 m, u32 fpscr)
|
||||
{
|
||||
struct vfp_single vsm;
|
||||
|
|
@ -684,14 +725,14 @@ static u32 vfp_single_ftosi(ARMul_State* state, int sd, int unused, s32 m, u32 f
|
|||
|
||||
if ((rem + incr) < rem && d < 0xffffffff)
|
||||
d += 1;
|
||||
if (d > 0x7fffffff + (vsm.sign != 0)) {
|
||||
d = 0x7fffffff + (vsm.sign != 0);
|
||||
if (d > (0x7fffffffu + (vsm.sign != 0))) {
|
||||
d = (0x7fffffffu + (vsm.sign != 0));
|
||||
exceptions |= FPSCR_IOC;
|
||||
} else if (rem)
|
||||
exceptions |= FPSCR_IXC;
|
||||
|
||||
if (vsm.sign)
|
||||
d = -d;
|
||||
d = 0-d;
|
||||
} else {
|
||||
d = 0;
|
||||
if (vsm.exponent | vsm.significand) {
|
||||
|
|
@ -800,7 +841,7 @@ vfp_single_add(struct vfp_single *vsd, struct vfp_single *vsn,
|
|||
|
||||
if (vsn->significand & 0x80000000 ||
|
||||
vsm->significand & 0x80000000) {
|
||||
pr_info("VFP: bad FP values\n");
|
||||
pr_info("VFP: bad FP values in %s\n", __func__);
|
||||
vfp_single_dump("VSN", vsn);
|
||||
vfp_single_dump("VSM", vsm);
|
||||
}
|
||||
|
|
@ -843,7 +884,7 @@ vfp_single_add(struct vfp_single *vsd, struct vfp_single *vsn,
|
|||
m_sig = vsn->significand - m_sig;
|
||||
if ((s32)m_sig < 0) {
|
||||
vsd->sign = vfp_sign_negate(vsd->sign);
|
||||
m_sig = -m_sig;
|
||||
m_sig = 0-m_sig;
|
||||
} else if (m_sig == 0) {
|
||||
vsd->sign = (fpscr & FPSCR_RMODE_MASK) ==
|
||||
FPSCR_ROUND_MINUSINF ? 0x8000 : 0;
|
||||
|
|
@ -917,12 +958,16 @@ vfp_single_multiply(struct vfp_single *vsd, struct vfp_single *vsn, struct vfp_s
|
|||
#define NEG_SUBTRACT (1 << 1)
|
||||
|
||||
static u32
|
||||
vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr, u32 negate, const char *func)
|
||||
vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr, u32 negate, char *func)
|
||||
{
|
||||
|
||||
{
|
||||
struct vfp_single vsd, vsp, vsn, vsm;
|
||||
u32 exceptions;
|
||||
s32 v;
|
||||
|
||||
|
||||
|
||||
v = vfp_get_float(state, sn);
|
||||
pr_debug("VFP: s%u = %08x\n", sn, v);
|
||||
vfp_single_unpack(&vsn, v);
|
||||
|
|
@ -934,6 +979,7 @@ vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s32 m, u32 fp
|
|||
vfp_single_normalise_denormal(&vsm);
|
||||
|
||||
exceptions = vfp_single_multiply(&vsp, &vsn, &vsm, fpscr);
|
||||
|
||||
if (negate & NEG_MULTIPLY)
|
||||
vsp.sign = vfp_sign_negate(vsp.sign);
|
||||
|
||||
|
|
@ -948,6 +994,38 @@ vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s32 m, u32 fp
|
|||
return vfp_single_normaliseround(state, sd, &vsd, fpscr, exceptions, func);
|
||||
}
|
||||
|
||||
struct vfp_double vsd, vsp, vsn, vsm;
|
||||
u32 exceptions;
|
||||
s32 v;
|
||||
s64 vd;
|
||||
s64 md;
|
||||
|
||||
v = vfp_get_float(state, sn);
|
||||
vd = vfp_single_to_doubleintern(state, v, fpscr);
|
||||
vfp_double_unpack(&vsn, vd);
|
||||
|
||||
md = vfp_single_to_doubleintern(state, m, fpscr);
|
||||
vfp_double_unpack(&vsm, md);
|
||||
|
||||
exceptions = vfp_double_multiply(&vsp, &vsn, &vsm, fpscr);
|
||||
if (negate & NEG_MULTIPLY)
|
||||
vsp.sign = vfp_sign_negate(vsp.sign);
|
||||
|
||||
v = vfp_get_float(state, sd);
|
||||
vd = vfp_single_to_doubleintern(state, v, fpscr);
|
||||
vfp_double_unpack(&vsn, vd);
|
||||
|
||||
if (negate & NEG_SUBTRACT)
|
||||
vsn.sign = vfp_sign_negate(vsn.sign);
|
||||
|
||||
exceptions |= vfp_double_add(&vsd, &vsn, &vsp, fpscr);
|
||||
|
||||
s64 debug = vfp_double_pack(&vsd);
|
||||
|
||||
return vfp_double_fcvtsinterncutting(state, sd, &vsd, fpscr);
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Standard operations
|
||||
*/
|
||||
|
|
@ -1148,7 +1226,7 @@ static u32 vfp_single_fdiv(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr)
|
|||
{
|
||||
u64 significand = (u64)vsn.significand << 32;
|
||||
do_div(significand, vsm.significand);
|
||||
vsd.significand = significand;
|
||||
vsd.significand = (u32)significand;
|
||||
}
|
||||
if ((vsd.significand & 0x3f) == 0)
|
||||
vsd.significand |= ((u64)vsm.significand * vsd.significand != (u64)vsn.significand << 32);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue