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	GPU: Fire GPU interrupts at the correct places.
PDC0 and PDC1 are both VBlank interrupts. PDC0 was being treated as a HBlank interrupt and fired many more times than it should. They now both fire together at 60 Hz. This puzzlingly *improves* apparent framerate on many applications. A few other interrupts were being fired inside the GSP command processing instead of on the actual GPU register writes, so they were moved there, which should cover direct writes tho those registers not going through the GX command queue.
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					 2 changed files with 18 additions and 21 deletions
				
			
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			@ -269,8 +269,6 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
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        WriteGPURegister(GPU_REG_INDEX(memory_fill_config[1].address_end), Memory::VirtualToPhysicalAddress(params.end2) >> 3);
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        WriteGPURegister(GPU_REG_INDEX(memory_fill_config[1].size), params.end2 - params.start2);
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        WriteGPURegister(GPU_REG_INDEX(memory_fill_config[1].value), params.value2);
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        SignalInterrupt(InterruptId::PSC0);
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        break;
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    }
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			@ -284,10 +282,6 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
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        WriteGPURegister(GPU_REG_INDEX(display_transfer_config.flags), params.flags);
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        WriteGPURegister(GPU_REG_INDEX(display_transfer_config.trigger), 1);
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        // TODO(bunnei): Determine if these interrupts should be signalled here.
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        SignalInterrupt(InterruptId::PSC1);
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        SignalInterrupt(InterruptId::PPF);
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        // Update framebuffer information if requested
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        for (int screen_id = 0; screen_id < 2; ++screen_id) {
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            FrameBufferUpdate* info = GetFrameBufferInfo(thread_id, screen_id);
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