Prefix all size_t with std::

done automatically by executing regex replace `([^:0-9a-zA-Z_])size_t([^0-9a-zA-Z_])` -> `$1std::size_t$2`

src/core/arm/arm_interface.h

@@ -20,12 +20,12 @@ public:
         virtual ~ThreadContext() = default;
 
         virtual void Reset() = 0;
-        virtual u32 GetCpuRegister(size_t index) const = 0;
-        virtual void SetCpuRegister(size_t index, u32 value) = 0;
+        virtual u32 GetCpuRegister(std::size_t index) const = 0;
+        virtual void SetCpuRegister(std::size_t index, u32 value) = 0;
         virtual u32 GetCpsr() const = 0;
         virtual void SetCpsr(u32 value) = 0;
-        virtual u32 GetFpuRegister(size_t index) const = 0;
-        virtual void SetFpuRegister(size_t index, u32 value) = 0;
+        virtual u32 GetFpuRegister(std::size_t index) const = 0;
+        virtual void SetFpuRegister(std::size_t index, u32 value) = 0;
         virtual u32 GetFpscr() const = 0;
         virtual void SetFpscr(u32 value) = 0;
         virtual u32 GetFpexc() const = 0;
@@ -67,7 +67,7 @@ public:
      * @param start_address The starting address of the range to invalidate.
      * @param length The length (in bytes) of the range to invalidate.
      */
-    virtual void InvalidateCacheRange(u32 start_address, size_t length) = 0;
+    virtual void InvalidateCacheRange(u32 start_address, std::size_t length) = 0;
 
     /// Notify CPU emulation that page tables have changed
     virtual void PageTableChanged() = 0;

src/core/arm/dynarmic/arm_dynarmic.cpp

@@ -30,10 +30,10 @@ public:
         fpexc = 0;
     }
 
-    u32 GetCpuRegister(size_t index) const override {
+    u32 GetCpuRegister(std::size_t index) const override {
         return ctx.Regs()[index];
     }
-    void SetCpuRegister(size_t index, u32 value) override {
+    void SetCpuRegister(std::size_t index, u32 value) override {
         ctx.Regs()[index] = value;
     }
     u32 GetCpsr() const override {
@@ -42,10 +42,10 @@ public:
     void SetCpsr(u32 value) override {
         ctx.SetCpsr(value);
     }
-    u32 GetFpuRegister(size_t index) const override {
+    u32 GetFpuRegister(std::size_t index) const override {
         return ctx.ExtRegs()[index];
     }
-    void SetFpuRegister(size_t index, u32 value) override {
+    void SetFpuRegister(std::size_t index, u32 value) override {
         ctx.ExtRegs()[index] = value;
     }
     u32 GetFpscr() const override {
@@ -99,7 +99,7 @@ public:
         Memory::Write64(vaddr, value);
     }
 
-    void InterpreterFallback(VAddr pc, size_t num_instructions) override {
+    void InterpreterFallback(VAddr pc, std::size_t num_instructions) override {
         parent.interpreter_state->Reg = parent.jit->Regs();
         parent.interpreter_state->Cpsr = parent.jit->Cpsr();
         parent.interpreter_state->Reg[15] = pc;
@@ -126,7 +126,7 @@ public:
 
     void ExceptionRaised(VAddr pc, Dynarmic::A32::Exception exception) override {
         ASSERT_MSG(false, "ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X})",
-                   static_cast<size_t>(exception), pc, MemoryReadCode(pc));
+                   static_cast<std::size_t>(exception), pc, MemoryReadCode(pc));
     }
 
     void AddTicks(std::uint64_t ticks) override {
@@ -253,7 +253,7 @@ void ARM_Dynarmic::ClearInstructionCache() {
     interpreter_state->instruction_cache.clear();
 }
 
-void ARM_Dynarmic::InvalidateCacheRange(u32 start_address, size_t length) {
+void ARM_Dynarmic::InvalidateCacheRange(u32 start_address, std::size_t length) {
     jit->InvalidateCacheRange(start_address, length);
 }
 

src/core/arm/dynarmic/arm_dynarmic.h

@@ -45,7 +45,7 @@ public:
     void PrepareReschedule() override;
 
     void ClearInstructionCache() override;
-    void InvalidateCacheRange(u32 start_address, size_t length) override;
+    void InvalidateCacheRange(u32 start_address, std::size_t length) override;
     void PageTableChanged() override;
 
 private:

src/core/arm/dyncom/arm_dyncom.cpp

@@ -27,10 +27,10 @@ public:
         fpexc = 0;
     }
 
-    u32 GetCpuRegister(size_t index) const override {
+    u32 GetCpuRegister(std::size_t index) const override {
         return cpu_registers[index];
     }
-    void SetCpuRegister(size_t index, u32 value) override {
+    void SetCpuRegister(std::size_t index, u32 value) override {
         cpu_registers[index] = value;
     }
     u32 GetCpsr() const override {
@@ -39,10 +39,10 @@ public:
     void SetCpsr(u32 value) override {
         cpsr = value;
     }
-    u32 GetFpuRegister(size_t index) const override {
+    u32 GetFpuRegister(std::size_t index) const override {
         return fpu_registers[index];
     }
-    void SetFpuRegister(size_t index, u32 value) override {
+    void SetFpuRegister(std::size_t index, u32 value) override {
         fpu_registers[index] = value;
     }
     u32 GetFpscr() const override {
@@ -87,7 +87,7 @@ void ARM_DynCom::ClearInstructionCache() {
     trans_cache_buf_top = 0;
 }
 
-void ARM_DynCom::InvalidateCacheRange(u32, size_t) {
+void ARM_DynCom::InvalidateCacheRange(u32, std::size_t) {
     ClearInstructionCache();
 }
 

src/core/arm/dyncom/arm_dyncom.h

@@ -19,7 +19,7 @@ public:
     void Step() override;
 
     void ClearInstructionCache() override;
-    void InvalidateCacheRange(u32 start_address, size_t length) override;
+    void InvalidateCacheRange(u32 start_address, std::size_t length) override;
     void PageTableChanged() override;
 
     void SetPC(u32 pc) override;

src/core/arm/dyncom/arm_dyncom_thumb.cpp

@@ -293,7 +293,7 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3
                 0xE6FF0FB0, // REVSH
             };
 
-            size_t subset_index = BITS(tinstr, 6, 7);
+            std::size_t subset_index = BITS(tinstr, 6, 7);
 
             if (subset_index == 2) {
                 valid = ThumbDecodeStatus::UNDEFINED;

src/core/arm/dyncom/arm_dyncom_trans.cpp

@@ -9,8 +9,8 @@
 char trans_cache_buf[TRANS_CACHE_SIZE];
 size_t trans_cache_buf_top = 0;
 
-static void* AllocBuffer(size_t size) {
-    size_t start = trans_cache_buf_top;
+static void* AllocBuffer(std::size_t size) {
+    std::size_t start = trans_cache_buf_top;
     trans_cache_buf_top += size;
     ASSERT_MSG(trans_cache_buf_top <= TRANS_CACHE_SIZE, "Translation cache is full!");
     return static_cast<void*>(&trans_cache_buf[start]);
@@ -2015,4 +2015,4 @@ const transop_fp_t arm_instruction_trans[] = {
     INTERPRETER_TRANSLATE(blx_1_thumb),
 };
 
-const size_t arm_instruction_trans_len = sizeof(arm_instruction_trans) / sizeof(transop_fp_t);
+const std::size_t arm_instruction_trans_len = sizeof(arm_instruction_trans) / sizeof(transop_fp_t);

src/core/arm/dyncom/arm_dyncom_trans.h

@@ -491,8 +491,8 @@ typedef arm_inst* ARM_INST_PTR;
 typedef ARM_INST_PTR (*transop_fp_t)(unsigned int, int);
 
 extern const transop_fp_t arm_instruction_trans[];
-extern const size_t arm_instruction_trans_len;
+extern const std::size_t arm_instruction_trans_len;
 
 #define TRANS_CACHE_SIZE (64 * 1024 * 2000)
 extern char trans_cache_buf[TRANS_CACHE_SIZE];
-extern size_t trans_cache_buf_top;
+extern std::size_t trans_cache_buf_top;