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ARM Core, Video Core, CitraQt, Citrace: Use CommonTypes types instead of the standard u?int*_t types.
This commit is contained in:
Emmanuel Gil Peyrot
parent
df25b047f8
commit
5115d0177e
8 changed files with 356 additions and 346 deletions
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@ -3,7 +3,9 @@
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#include <string>
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#include <unordered_set>
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#include "common/common_types.h"
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#include "common/string_util.h"
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#include "core/arm/disassembler/arm_disasm.h"
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#include "core/arm/skyeye_common/armsupp.h"
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@ -215,11 +217,11 @@ static const char *shift_names[] = {
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"ROR"
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};
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static const char* cond_to_str(uint32_t cond) {
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static const char* cond_to_str(u32 cond) {
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return cond_names[cond];
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}
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std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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std::string ARM_Disasm::Disassemble(u32 addr, u32 insn)
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{
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Opcode opcode = Decode(insn);
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switch (opcode) {
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@ -400,22 +402,22 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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return NULL;
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}
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std::string ARM_Disasm::DisassembleALU(Opcode opcode, uint32_t insn)
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std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn)
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{
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static const uint8_t kNoOperand1 = 1;
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static const uint8_t kNoDest = 2;
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static const uint8_t kNoSbit = 4;
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static const u8 kNoOperand1 = 1;
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static const u8 kNoDest = 2;
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static const u8 kNoSbit = 4;
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std::string rn_str;
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std::string rd_str;
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uint8_t flags = 0;
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t is_immed = (insn >> 25) & 0x1;
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uint8_t bit_s = (insn >> 20) & 1;
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uint8_t rn = (insn >> 16) & 0xf;
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uint8_t rd = (insn >> 12) & 0xf;
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uint8_t immed = insn & 0xff;
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u8 flags = 0;
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u8 cond = (insn >> 28) & 0xf;
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u8 is_immed = (insn >> 25) & 0x1;
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u8 bit_s = (insn >> 20) & 1;
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u8 rn = (insn >> 16) & 0xf;
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u8 rd = (insn >> 12) & 0xf;
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u8 immed = insn & 0xff;
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const char* opname = opcode_names[opcode];
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switch (opcode) {
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@ -455,14 +457,14 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, uint32_t insn)
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), immed, immed);
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}
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uint8_t shift_is_reg = (insn >> 4) & 1;
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uint8_t rotate = (insn >> 8) & 0xf;
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uint8_t rm = insn & 0xf;
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uint8_t shift_type = (insn >> 5) & 0x3;
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uint8_t rs = (insn >> 8) & 0xf;
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uint8_t shift_amount = (insn >> 7) & 0x1f;
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uint32_t rotated_val = immed;
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uint8_t rotate2 = rotate << 1;
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u8 shift_is_reg = (insn >> 4) & 1;
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u8 rotate = (insn >> 8) & 0xf;
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u8 rm = insn & 0xf;
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u8 shift_type = (insn >> 5) & 0x3;
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u8 rs = (insn >> 8) & 0xf;
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u8 shift_amount = (insn >> 7) & 0x1f;
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u32 rotated_val = immed;
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u8 rotate2 = rotate << 1;
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rotated_val = (rotated_val >> rotate2) | (rotated_val << (32 - rotate2));
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if (!shift_is_reg && shift_type == 0 && shift_amount == 0) {
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@ -488,10 +490,10 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, uint32_t insn)
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shift_name, shift_amount);
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}
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std::string ARM_Disasm::DisassembleBranch(uint32_t addr, Opcode opcode, uint32_t insn)
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std::string ARM_Disasm::DisassembleBranch(u32 addr, Opcode opcode, u32 insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint32_t offset = insn & 0xffffff;
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u8 cond = (insn >> 28) & 0xf;
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u32 offset = insn & 0xffffff;
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// Sign-extend the 24-bit offset
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if ((offset >> 23) & 1)
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offset |= 0xff000000;
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@ -504,35 +506,35 @@ std::string ARM_Disasm::DisassembleBranch(uint32_t addr, Opcode opcode, uint32_t
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return Common::StringFromFormat("%s%s\t0x%x", opname, cond_to_str(cond), addr);
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}
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std::string ARM_Disasm::DisassembleBX(uint32_t insn)
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std::string ARM_Disasm::DisassembleBX(u32 insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t rn = insn & 0xf;
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u8 cond = (insn >> 28) & 0xf;
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u8 rn = insn & 0xf;
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return Common::StringFromFormat("bx%s\tr%d", cond_to_str(cond), rn);
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}
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std::string ARM_Disasm::DisassembleBKPT(uint32_t insn)
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std::string ARM_Disasm::DisassembleBKPT(u32 insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint32_t immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf);
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u8 cond = (insn >> 28) & 0xf;
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u32 immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf);
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return Common::StringFromFormat("bkpt%s\t#%d", cond_to_str(cond), immed);
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}
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std::string ARM_Disasm::DisassembleCLZ(uint32_t insn)
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std::string ARM_Disasm::DisassembleCLZ(u32 insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t rd = (insn >> 12) & 0xf;
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uint8_t rm = insn & 0xf;
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u8 cond = (insn >> 28) & 0xf;
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u8 rd = (insn >> 12) & 0xf;
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u8 rm = insn & 0xf;
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return Common::StringFromFormat("clz%s\tr%d, r%d", cond_to_str(cond), rd, rm);
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}
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std::string ARM_Disasm::DisassembleMediaMulDiv(Opcode opcode, uint32_t insn) {
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uint32_t cond = BITS(insn, 28, 31);
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uint32_t rd = BITS(insn, 16, 19);
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uint32_t ra = BITS(insn, 12, 15);
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uint32_t rm = BITS(insn, 8, 11);
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uint32_t m = BIT(insn, 5);
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uint32_t rn = BITS(insn, 0, 3);
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std::string ARM_Disasm::DisassembleMediaMulDiv(Opcode opcode, u32 insn) {
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u32 cond = BITS(insn, 28, 31);
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u32 rd = BITS(insn, 16, 19);
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u32 ra = BITS(insn, 12, 15);
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u32 rm = BITS(insn, 8, 11);
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u32 m = BIT(insn, 5);
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u32 rn = BITS(insn, 0, 3);
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std::string cross = "";
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if (m) {
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@ -558,17 +560,17 @@ std::string ARM_Disasm::DisassembleMediaMulDiv(Opcode opcode, uint32_t insn) {
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ext_reg.c_str());
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}
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std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, uint32_t insn)
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std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn)
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{
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std::string tmp_list;
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t write_back = (insn >> 21) & 0x1;
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uint8_t bit_s = (insn >> 22) & 0x1;
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uint8_t is_up = (insn >> 23) & 0x1;
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uint8_t is_pre = (insn >> 24) & 0x1;
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uint8_t rn = (insn >> 16) & 0xf;
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uint16_t reg_list = insn & 0xffff;
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u8 cond = (insn >> 28) & 0xf;
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u8 write_back = (insn >> 21) & 0x1;
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u8 bit_s = (insn >> 22) & 0x1;
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u8 is_up = (insn >> 23) & 0x1;
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u8 is_pre = (insn >> 24) & 0x1;
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u8 rn = (insn >> 16) & 0xf;
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u16 reg_list = insn & 0xffff;
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const char *opname = opcode_names[opcode];
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@ -608,18 +610,18 @@ std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, uint32_t insn)
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opname, cond_to_str(cond), addr_mode, rn, bang, tmp_list.c_str(), carret);
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}
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std::string ARM_Disasm::DisassembleMem(uint32_t insn)
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std::string ARM_Disasm::DisassembleMem(u32 insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t is_reg = (insn >> 25) & 0x1;
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uint8_t is_load = (insn >> 20) & 0x1;
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uint8_t write_back = (insn >> 21) & 0x1;
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uint8_t is_byte = (insn >> 22) & 0x1;
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uint8_t is_up = (insn >> 23) & 0x1;
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uint8_t is_pre = (insn >> 24) & 0x1;
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uint8_t rn = (insn >> 16) & 0xf;
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uint8_t rd = (insn >> 12) & 0xf;
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uint16_t offset = insn & 0xfff;
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u8 cond = (insn >> 28) & 0xf;
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u8 is_reg = (insn >> 25) & 0x1;
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u8 is_load = (insn >> 20) & 0x1;
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u8 write_back = (insn >> 21) & 0x1;
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u8 is_byte = (insn >> 22) & 0x1;
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u8 is_up = (insn >> 23) & 0x1;
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u8 is_pre = (insn >> 24) & 0x1;
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u8 rn = (insn >> 16) & 0xf;
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u8 rd = (insn >> 12) & 0xf;
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u16 offset = insn & 0xfff;
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const char *opname = "ldr";
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if (!is_load)
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@ -656,9 +658,9 @@ std::string ARM_Disasm::DisassembleMem(uint32_t insn)
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}
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}
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uint8_t rm = insn & 0xf;
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uint8_t shift_type = (insn >> 5) & 0x3;
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uint8_t shift_amount = (insn >> 7) & 0x1f;
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u8 rm = insn & 0xf;
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u8 shift_type = (insn >> 5) & 0x3;
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u8 shift_amount = (insn >> 7) & 0x1f;
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const char *shift_name = shift_names[shift_type];
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@ -700,19 +702,19 @@ std::string ARM_Disasm::DisassembleMem(uint32_t insn)
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shift_name, shift_amount);
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}
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std::string ARM_Disasm::DisassembleMemHalf(uint32_t insn)
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std::string ARM_Disasm::DisassembleMemHalf(u32 insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t is_load = (insn >> 20) & 0x1;
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uint8_t write_back = (insn >> 21) & 0x1;
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uint8_t is_immed = (insn >> 22) & 0x1;
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uint8_t is_up = (insn >> 23) & 0x1;
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uint8_t is_pre = (insn >> 24) & 0x1;
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uint8_t rn = (insn >> 16) & 0xf;
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uint8_t rd = (insn >> 12) & 0xf;
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uint8_t bits_65 = (insn >> 5) & 0x3;
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uint8_t rm = insn & 0xf;
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uint8_t offset = (((insn >> 8) & 0xf) << 4) | (insn & 0xf);
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u8 cond = (insn >> 28) & 0xf;
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u8 is_load = (insn >> 20) & 0x1;
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u8 write_back = (insn >> 21) & 0x1;
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u8 is_immed = (insn >> 22) & 0x1;
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u8 is_up = (insn >> 23) & 0x1;
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u8 is_pre = (insn >> 24) & 0x1;
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u8 rn = (insn >> 16) & 0xf;
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u8 rd = (insn >> 12) & 0xf;
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u8 bits_65 = (insn >> 5) & 0x3;
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u8 rm = insn & 0xf;
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u8 offset = (((insn >> 8) & 0xf) << 4) | (insn & 0xf);
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const char *opname = "ldr";
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if (is_load == 0)
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@ -756,78 +758,78 @@ std::string ARM_Disasm::DisassembleMemHalf(uint32_t insn)
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}
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}
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std::string ARM_Disasm::DisassembleMCR(Opcode opcode, uint32_t insn)
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std::string ARM_Disasm::DisassembleMCR(Opcode opcode, u32 insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t crn = (insn >> 16) & 0xf;
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uint8_t crd = (insn >> 12) & 0xf;
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uint8_t cpnum = (insn >> 8) & 0xf;
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uint8_t opcode2 = (insn >> 5) & 0x7;
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uint8_t crm = insn & 0xf;
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u8 cond = (insn >> 28) & 0xf;
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u8 crn = (insn >> 16) & 0xf;
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u8 crd = (insn >> 12) & 0xf;
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u8 cpnum = (insn >> 8) & 0xf;
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u8 opcode2 = (insn >> 5) & 0x7;
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u8 crm = insn & 0xf;
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const char *opname = opcode_names[opcode];
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return Common::StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}",
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opname, cond_to_str(cond), cpnum, crd, crn, crm, opcode2);
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}
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std::string ARM_Disasm::DisassembleMLA(Opcode opcode, uint32_t insn)
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std::string ARM_Disasm::DisassembleMLA(Opcode opcode, u32 insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t rd = (insn >> 16) & 0xf;
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uint8_t rn = (insn >> 12) & 0xf;
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uint8_t rs = (insn >> 8) & 0xf;
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uint8_t rm = insn & 0xf;
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uint8_t bit_s = (insn >> 20) & 1;
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u8 cond = (insn >> 28) & 0xf;
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u8 rd = (insn >> 16) & 0xf;
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u8 rn = (insn >> 12) & 0xf;
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u8 rs = (insn >> 8) & 0xf;
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u8 rm = insn & 0xf;
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u8 bit_s = (insn >> 20) & 1;
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const char *opname = opcode_names[opcode];
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return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d",
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opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs, rn);
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}
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std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, uint32_t insn)
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std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, u32 insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t rdhi = (insn >> 16) & 0xf;
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uint8_t rdlo = (insn >> 12) & 0xf;
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uint8_t rs = (insn >> 8) & 0xf;
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uint8_t rm = insn & 0xf;
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uint8_t bit_s = (insn >> 20) & 1;
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u8 cond = (insn >> 28) & 0xf;
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u8 rdhi = (insn >> 16) & 0xf;
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u8 rdlo = (insn >> 12) & 0xf;
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u8 rs = (insn >> 8) & 0xf;
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u8 rm = insn & 0xf;
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u8 bit_s = (insn >> 20) & 1;
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const char *opname = opcode_names[opcode];
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return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d",
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opname, cond_to_str(cond), bit_s ? "s" : "", rdlo, rdhi, rm, rs);
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}
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std::string ARM_Disasm::DisassembleMUL(Opcode opcode, uint32_t insn)
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std::string ARM_Disasm::DisassembleMUL(Opcode opcode, u32 insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t rd = (insn >> 16) & 0xf;
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uint8_t rs = (insn >> 8) & 0xf;
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uint8_t rm = insn & 0xf;
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uint8_t bit_s = (insn >> 20) & 1;
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u8 cond = (insn >> 28) & 0xf;
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u8 rd = (insn >> 16) & 0xf;
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u8 rs = (insn >> 8) & 0xf;
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u8 rm = insn & 0xf;
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u8 bit_s = (insn >> 20) & 1;
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const char *opname = opcode_names[opcode];
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return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d",
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opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs);
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}
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std::string ARM_Disasm::DisassembleMRS(uint32_t insn)
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std::string ARM_Disasm::DisassembleMRS(u32 insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t rd = (insn >> 12) & 0xf;
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uint8_t ps = (insn >> 22) & 1;
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u8 cond = (insn >> 28) & 0xf;
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u8 rd = (insn >> 12) & 0xf;
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u8 ps = (insn >> 22) & 1;
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return Common::StringFromFormat("mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr");
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}
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std::string ARM_Disasm::DisassembleMSR(uint32_t insn)
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std::string ARM_Disasm::DisassembleMSR(u32 insn)
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{
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char flags[8];
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int flag_index = 0;
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t is_immed = (insn >> 25) & 0x1;
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uint8_t pd = (insn >> 22) & 1;
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uint8_t mask = (insn >> 16) & 0xf;
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u8 cond = (insn >> 28) & 0xf;
|
||||
u8 is_immed = (insn >> 25) & 0x1;
|
||||
u8 pd = (insn >> 22) & 1;
|
||||
u8 mask = (insn >> 16) & 0xf;
|
||||
|
||||
if (mask & 1)
|
||||
flags[flag_index++] = 'c';
|
||||
|
|
@ -840,44 +842,44 @@ std::string ARM_Disasm::DisassembleMSR(uint32_t insn)
|
|||
flags[flag_index] = 0;
|
||||
|
||||
if (is_immed) {
|
||||
uint32_t immed = insn & 0xff;
|
||||
uint8_t rotate = (insn >> 8) & 0xf;
|
||||
uint8_t rotate2 = rotate << 1;
|
||||
uint32_t rotated_val = (immed >> rotate2) | (immed << (32 - rotate2));
|
||||
u32 immed = insn & 0xff;
|
||||
u8 rotate = (insn >> 8) & 0xf;
|
||||
u8 rotate2 = rotate << 1;
|
||||
u32 rotated_val = (immed >> rotate2) | (immed << (32 - rotate2));
|
||||
return Common::StringFromFormat("msr%s\t%s_%s, #0x%x",
|
||||
cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rotated_val);
|
||||
}
|
||||
|
||||
uint8_t rm = insn & 0xf;
|
||||
u8 rm = insn & 0xf;
|
||||
|
||||
return Common::StringFromFormat("msr%s\t%s_%s, r%d",
|
||||
cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rm);
|
||||
}
|
||||
|
||||
std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, uint32_t insn)
|
||||
std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, u32 insn)
|
||||
{
|
||||
uint32_t cond = BITS(insn, 28, 31);
|
||||
u32 cond = BITS(insn, 28, 31);
|
||||
return Common::StringFromFormat("%s%s", opcode_names[opcode], cond_to_str(cond));
|
||||
}
|
||||
|
||||
std::string ARM_Disasm::DisassembleParallelAddSub(Opcode opcode, uint32_t insn) {
|
||||
uint32_t cond = BITS(insn, 28, 31);
|
||||
uint32_t rn = BITS(insn, 16, 19);
|
||||
uint32_t rd = BITS(insn, 12, 15);
|
||||
uint32_t rm = BITS(insn, 0, 3);
|
||||
std::string ARM_Disasm::DisassembleParallelAddSub(Opcode opcode, u32 insn) {
|
||||
u32 cond = BITS(insn, 28, 31);
|
||||
u32 rn = BITS(insn, 16, 19);
|
||||
u32 rd = BITS(insn, 12, 15);
|
||||
u32 rm = BITS(insn, 0, 3);
|
||||
|
||||
return Common::StringFromFormat("%s%s\tr%u, r%u, r%u", opcode_names[opcode], cond_to_str(cond),
|
||||
rd, rn, rm);
|
||||
}
|
||||
|
||||
std::string ARM_Disasm::DisassemblePKH(uint32_t insn)
|
||||
std::string ARM_Disasm::DisassemblePKH(u32 insn)
|
||||
{
|
||||
uint32_t cond = BITS(insn, 28, 31);
|
||||
uint32_t rn = BITS(insn, 16, 19);
|
||||
uint32_t rd = BITS(insn, 12, 15);
|
||||
uint32_t imm5 = BITS(insn, 7, 11);
|
||||
uint32_t tb = BIT(insn, 6);
|
||||
uint32_t rm = BITS(insn, 0, 3);
|
||||
u32 cond = BITS(insn, 28, 31);
|
||||
u32 rn = BITS(insn, 16, 19);
|
||||
u32 rd = BITS(insn, 12, 15);
|
||||
u32 imm5 = BITS(insn, 7, 11);
|
||||
u32 tb = BIT(insn, 6);
|
||||
u32 rm = BITS(insn, 0, 3);
|
||||
|
||||
std::string suffix = tb ? "tb" : "bt";
|
||||
std::string shift = "";
|
||||
|
|
@ -894,22 +896,22 @@ std::string ARM_Disasm::DisassemblePKH(uint32_t insn)
|
|||
rd, rn, rm, shift.c_str());
|
||||
}
|
||||
|
||||
std::string ARM_Disasm::DisassemblePLD(uint32_t insn)
|
||||
std::string ARM_Disasm::DisassemblePLD(u32 insn)
|
||||
{
|
||||
uint8_t is_reg = (insn >> 25) & 0x1;
|
||||
uint8_t is_up = (insn >> 23) & 0x1;
|
||||
uint8_t rn = (insn >> 16) & 0xf;
|
||||
u8 is_reg = (insn >> 25) & 0x1;
|
||||
u8 is_up = (insn >> 23) & 0x1;
|
||||
u8 rn = (insn >> 16) & 0xf;
|
||||
|
||||
const char *minus = "";
|
||||
if (is_up == 0)
|
||||
minus = "-";
|
||||
|
||||
if (is_reg) {
|
||||
uint8_t rm = insn & 0xf;
|
||||
u8 rm = insn & 0xf;
|
||||
return Common::StringFromFormat("pld\t[r%d, %sr%d]", rn, minus, rm);
|
||||
}
|
||||
|
||||
uint16_t offset = insn & 0xfff;
|
||||
u16 offset = insn & 0xfff;
|
||||
if (offset == 0) {
|
||||
return Common::StringFromFormat("pld\t[r%d]", rn);
|
||||
} else {
|
||||
|
|
@ -917,20 +919,20 @@ std::string ARM_Disasm::DisassemblePLD(uint32_t insn)
|
|||
}
|
||||
}
|
||||
|
||||
std::string ARM_Disasm::DisassembleREV(Opcode opcode, uint32_t insn) {
|
||||
uint32_t cond = BITS(insn, 28, 31);
|
||||
uint32_t rd = BITS(insn, 12, 15);
|
||||
uint32_t rm = BITS(insn, 0, 3);
|
||||
std::string ARM_Disasm::DisassembleREV(Opcode opcode, u32 insn) {
|
||||
u32 cond = BITS(insn, 28, 31);
|
||||
u32 rd = BITS(insn, 12, 15);
|
||||
u32 rm = BITS(insn, 0, 3);
|
||||
|
||||
return Common::StringFromFormat("%s%s\tr%u, r%u", opcode_names[opcode], cond_to_str(cond),
|
||||
rd, rm);
|
||||
}
|
||||
|
||||
std::string ARM_Disasm::DisassembleREX(Opcode opcode, uint32_t insn) {
|
||||
uint32_t rn = BITS(insn, 16, 19);
|
||||
uint32_t rd = BITS(insn, 12, 15);
|
||||
uint32_t rt = BITS(insn, 0, 3);
|
||||
uint32_t cond = BITS(insn, 28, 31);
|
||||
std::string ARM_Disasm::DisassembleREX(Opcode opcode, u32 insn) {
|
||||
u32 rn = BITS(insn, 16, 19);
|
||||
u32 rd = BITS(insn, 12, 15);
|
||||
u32 rt = BITS(insn, 0, 3);
|
||||
u32 cond = BITS(insn, 28, 31);
|
||||
|
||||
switch (opcode) {
|
||||
case OP_STREX:
|
||||
|
|
@ -956,13 +958,13 @@ std::string ARM_Disasm::DisassembleREX(Opcode opcode, uint32_t insn) {
|
|||
}
|
||||
}
|
||||
|
||||
std::string ARM_Disasm::DisassembleSAT(Opcode opcode, uint32_t insn) {
|
||||
uint32_t cond = BITS(insn, 28, 31);
|
||||
uint32_t sat_imm = BITS(insn, 16, 20);
|
||||
uint32_t rd = BITS(insn, 12, 15);
|
||||
uint32_t imm5 = BITS(insn, 7, 11);
|
||||
uint32_t sh = BIT(insn, 6);
|
||||
uint32_t rn = BITS(insn, 0, 3);
|
||||
std::string ARM_Disasm::DisassembleSAT(Opcode opcode, u32 insn) {
|
||||
u32 cond = BITS(insn, 28, 31);
|
||||
u32 sat_imm = BITS(insn, 16, 20);
|
||||
u32 rd = BITS(insn, 12, 15);
|
||||
u32 imm5 = BITS(insn, 7, 11);
|
||||
u32 sh = BIT(insn, 6);
|
||||
u32 rn = BITS(insn, 0, 3);
|
||||
|
||||
std::string shift_part = "";
|
||||
bool opcode_has_shift = (opcode == OP_SSAT) || (opcode == OP_USAT);
|
||||
|
|
@ -984,42 +986,42 @@ std::string ARM_Disasm::DisassembleSAT(Opcode opcode, uint32_t insn) {
|
|||
sat_imm, rn, shift_part.c_str());
|
||||
}
|
||||
|
||||
std::string ARM_Disasm::DisassembleSEL(uint32_t insn) {
|
||||
uint32_t cond = BITS(insn, 28, 31);
|
||||
uint32_t rn = BITS(insn, 16, 19);
|
||||
uint32_t rd = BITS(insn, 12, 15);
|
||||
uint32_t rm = BITS(insn, 0, 3);
|
||||
std::string ARM_Disasm::DisassembleSEL(u32 insn) {
|
||||
u32 cond = BITS(insn, 28, 31);
|
||||
u32 rn = BITS(insn, 16, 19);
|
||||
u32 rd = BITS(insn, 12, 15);
|
||||
u32 rm = BITS(insn, 0, 3);
|
||||
|
||||
return Common::StringFromFormat("%s%s\tr%u, r%u, r%u", opcode_names[OP_SEL], cond_to_str(cond),
|
||||
rd, rn, rm);
|
||||
}
|
||||
|
||||
std::string ARM_Disasm::DisassembleSWI(uint32_t insn)
|
||||
std::string ARM_Disasm::DisassembleSWI(u32 insn)
|
||||
{
|
||||
uint8_t cond = (insn >> 28) & 0xf;
|
||||
uint32_t sysnum = insn & 0x00ffffff;
|
||||
u8 cond = (insn >> 28) & 0xf;
|
||||
u32 sysnum = insn & 0x00ffffff;
|
||||
|
||||
return Common::StringFromFormat("swi%s 0x%x", cond_to_str(cond), sysnum);
|
||||
}
|
||||
|
||||
std::string ARM_Disasm::DisassembleSWP(Opcode opcode, uint32_t insn)
|
||||
std::string ARM_Disasm::DisassembleSWP(Opcode opcode, u32 insn)
|
||||
{
|
||||
uint8_t cond = (insn >> 28) & 0xf;
|
||||
uint8_t rn = (insn >> 16) & 0xf;
|
||||
uint8_t rd = (insn >> 12) & 0xf;
|
||||
uint8_t rm = insn & 0xf;
|
||||
u8 cond = (insn >> 28) & 0xf;
|
||||
u8 rn = (insn >> 16) & 0xf;
|
||||
u8 rd = (insn >> 12) & 0xf;
|
||||
u8 rm = insn & 0xf;
|
||||
|
||||
const char *opname = opcode_names[opcode];
|
||||
return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn);
|
||||
}
|
||||
|
||||
std::string ARM_Disasm::DisassembleXT(Opcode opcode, uint32_t insn)
|
||||
std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn)
|
||||
{
|
||||
uint32_t cond = BITS(insn, 28, 31);
|
||||
uint32_t rn = BITS(insn, 16, 19);
|
||||
uint32_t rd = BITS(insn, 12, 15);
|
||||
uint32_t rotate = BITS(insn, 10, 11);
|
||||
uint32_t rm = BITS(insn, 0, 3);
|
||||
u32 cond = BITS(insn, 28, 31);
|
||||
u32 rn = BITS(insn, 16, 19);
|
||||
u32 rd = BITS(insn, 12, 15);
|
||||
u32 rotate = BITS(insn, 10, 11);
|
||||
u32 rm = BITS(insn, 0, 3);
|
||||
|
||||
std::string rn_part = "";
|
||||
static std::unordered_set<Opcode, std::hash<int>> extend_with_add = {
|
||||
|
|
@ -1037,8 +1039,8 @@ std::string ARM_Disasm::DisassembleXT(Opcode opcode, uint32_t insn)
|
|||
rd, rn_part.c_str(), rm, rotate_part.c_str());
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::Decode(uint32_t insn) {
|
||||
uint32_t bits27_26 = (insn >> 26) & 0x3;
|
||||
Opcode ARM_Disasm::Decode(u32 insn) {
|
||||
u32 bits27_26 = (insn >> 26) & 0x3;
|
||||
switch (bits27_26) {
|
||||
case 0x0:
|
||||
return Decode00(insn);
|
||||
|
|
@ -1052,9 +1054,9 @@ Opcode ARM_Disasm::Decode(uint32_t insn) {
|
|||
return OP_INVALID;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::Decode00(uint32_t insn) {
|
||||
uint8_t bit25 = (insn >> 25) & 0x1;
|
||||
uint8_t bit4 = (insn >> 4) & 0x1;
|
||||
Opcode ARM_Disasm::Decode00(u32 insn) {
|
||||
u8 bit25 = (insn >> 25) & 0x1;
|
||||
u8 bit4 = (insn >> 4) & 0x1;
|
||||
if (bit25 == 0 && bit4 == 1) {
|
||||
if ((insn & 0x0ffffff0) == 0x012fff10) {
|
||||
// Bx instruction
|
||||
|
|
@ -1068,9 +1070,9 @@ Opcode ARM_Disasm::Decode00(uint32_t insn) {
|
|||
// Bkpt instruction
|
||||
return OP_BKPT;
|
||||
}
|
||||
uint32_t bits7_4 = (insn >> 4) & 0xf;
|
||||
u32 bits7_4 = (insn >> 4) & 0xf;
|
||||
if (bits7_4 == 0x9) {
|
||||
uint32_t bit24 = BIT(insn, 24);
|
||||
u32 bit24 = BIT(insn, 24);
|
||||
if (bit24) {
|
||||
return DecodeSyncPrimitive(insn);
|
||||
}
|
||||
|
|
@ -1078,14 +1080,14 @@ Opcode ARM_Disasm::Decode00(uint32_t insn) {
|
|||
return DecodeMUL(insn);
|
||||
}
|
||||
|
||||
uint8_t bit7 = (insn >> 7) & 0x1;
|
||||
u8 bit7 = (insn >> 7) & 0x1;
|
||||
if (bit7 == 1) {
|
||||
// One of the load/store halfword/byte instructions
|
||||
return DecodeLDRH(insn);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t op1 = BITS(insn, 20, 24);
|
||||
u32 op1 = BITS(insn, 20, 24);
|
||||
if (bit25 && (op1 == 0x12 || op1 == 0x16)) {
|
||||
// One of the MSR (immediate) and hints instructions
|
||||
return DecodeMSRImmAndHints(insn);
|
||||
|
|
@ -1095,13 +1097,13 @@ Opcode ARM_Disasm::Decode00(uint32_t insn) {
|
|||
return DecodeALU(insn);
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::Decode01(uint32_t insn) {
|
||||
uint8_t is_reg = (insn >> 25) & 0x1;
|
||||
uint8_t bit4 = (insn >> 4) & 0x1;
|
||||
Opcode ARM_Disasm::Decode01(u32 insn) {
|
||||
u8 is_reg = (insn >> 25) & 0x1;
|
||||
u8 bit4 = (insn >> 4) & 0x1;
|
||||
if (is_reg == 1 && bit4 == 1)
|
||||
return DecodeMedia(insn);
|
||||
uint8_t is_load = (insn >> 20) & 0x1;
|
||||
uint8_t is_byte = (insn >> 22) & 0x1;
|
||||
u8 is_load = (insn >> 20) & 0x1;
|
||||
u8 is_byte = (insn >> 22) & 0x1;
|
||||
if ((insn & 0xfd70f000) == 0xf550f000) {
|
||||
// Pre-load
|
||||
return OP_PLD;
|
||||
|
|
@ -1126,11 +1128,11 @@ Opcode ARM_Disasm::Decode01(uint32_t insn) {
|
|||
return OP_STR;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::Decode10(uint32_t insn) {
|
||||
uint8_t bit25 = (insn >> 25) & 0x1;
|
||||
Opcode ARM_Disasm::Decode10(u32 insn) {
|
||||
u8 bit25 = (insn >> 25) & 0x1;
|
||||
if (bit25 == 0) {
|
||||
// LDM/STM
|
||||
uint8_t is_load = (insn >> 20) & 0x1;
|
||||
u8 is_load = (insn >> 20) & 0x1;
|
||||
if (is_load)
|
||||
return OP_LDM;
|
||||
return OP_STM;
|
||||
|
|
@ -1143,11 +1145,11 @@ Opcode ARM_Disasm::Decode10(uint32_t insn) {
|
|||
return OP_B;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::Decode11(uint32_t insn) {
|
||||
uint8_t bit25 = (insn >> 25) & 0x1;
|
||||
Opcode ARM_Disasm::Decode11(u32 insn) {
|
||||
u8 bit25 = (insn >> 25) & 0x1;
|
||||
if (bit25 == 0) {
|
||||
// LDC, SDC
|
||||
uint8_t is_load = (insn >> 20) & 0x1;
|
||||
u8 is_load = (insn >> 20) & 0x1;
|
||||
if (is_load) {
|
||||
// LDC
|
||||
return OP_LDC;
|
||||
|
|
@ -1156,18 +1158,18 @@ Opcode ARM_Disasm::Decode11(uint32_t insn) {
|
|||
return OP_STC;
|
||||
}
|
||||
|
||||
uint8_t bit24 = (insn >> 24) & 0x1;
|
||||
u8 bit24 = (insn >> 24) & 0x1;
|
||||
if (bit24 == 0x1) {
|
||||
// SWI
|
||||
return OP_SWI;
|
||||
}
|
||||
|
||||
uint8_t bit4 = (insn >> 4) & 0x1;
|
||||
uint8_t cpnum = (insn >> 8) & 0xf;
|
||||
u8 bit4 = (insn >> 4) & 0x1;
|
||||
u8 cpnum = (insn >> 8) & 0xf;
|
||||
|
||||
if (cpnum == 15) {
|
||||
// Special case for coprocessor 15
|
||||
uint8_t opcode = (insn >> 21) & 0x7;
|
||||
u8 opcode = (insn >> 21) & 0x7;
|
||||
if (bit4 == 0 || opcode != 0) {
|
||||
// This is an unexpected bit pattern. Create an undefined
|
||||
// instruction in case this is ever executed.
|
||||
|
|
@ -1175,7 +1177,7 @@ Opcode ARM_Disasm::Decode11(uint32_t insn) {
|
|||
}
|
||||
|
||||
// MRC, MCR
|
||||
uint8_t is_mrc = (insn >> 20) & 0x1;
|
||||
u8 is_mrc = (insn >> 20) & 0x1;
|
||||
if (is_mrc)
|
||||
return OP_MRC;
|
||||
return OP_MCR;
|
||||
|
|
@ -1186,15 +1188,15 @@ Opcode ARM_Disasm::Decode11(uint32_t insn) {
|
|||
return OP_CDP;
|
||||
}
|
||||
// MRC, MCR
|
||||
uint8_t is_mrc = (insn >> 20) & 0x1;
|
||||
u8 is_mrc = (insn >> 20) & 0x1;
|
||||
if (is_mrc)
|
||||
return OP_MRC;
|
||||
return OP_MCR;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::DecodeSyncPrimitive(uint32_t insn) {
|
||||
uint32_t op = BITS(insn, 20, 23);
|
||||
uint32_t bit22 = BIT(insn, 22);
|
||||
Opcode ARM_Disasm::DecodeSyncPrimitive(u32 insn) {
|
||||
u32 op = BITS(insn, 20, 23);
|
||||
u32 bit22 = BIT(insn, 22);
|
||||
switch (op) {
|
||||
case 0x0:
|
||||
if (bit22)
|
||||
|
|
@ -1221,10 +1223,10 @@ Opcode ARM_Disasm::DecodeSyncPrimitive(uint32_t insn) {
|
|||
}
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::DecodeParallelAddSub(uint32_t insn) {
|
||||
uint32_t op1 = BITS(insn, 20, 21);
|
||||
uint32_t op2 = BITS(insn, 5, 7);
|
||||
uint32_t is_unsigned = BIT(insn, 22);
|
||||
Opcode ARM_Disasm::DecodeParallelAddSub(u32 insn) {
|
||||
u32 op1 = BITS(insn, 20, 21);
|
||||
u32 op2 = BITS(insn, 5, 7);
|
||||
u32 is_unsigned = BIT(insn, 22);
|
||||
|
||||
if (op1 == 0x0 || op2 == 0x5 || op2 == 0x6)
|
||||
return OP_UNDEFINED;
|
||||
|
|
@ -1260,14 +1262,14 @@ Opcode ARM_Disasm::DecodeParallelAddSub(uint32_t insn) {
|
|||
OP_SHSUB8, OP_UHSUB8
|
||||
};
|
||||
|
||||
uint32_t opcode_index = op1 * 12 + op2 * 2 + is_unsigned;
|
||||
u32 opcode_index = op1 * 12 + op2 * 2 + is_unsigned;
|
||||
return opcodes[opcode_index];
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::DecodePackingSaturationReversal(uint32_t insn) {
|
||||
uint32_t op1 = BITS(insn, 20, 22);
|
||||
uint32_t a = BITS(insn, 16, 19);
|
||||
uint32_t op2 = BITS(insn, 5, 7);
|
||||
Opcode ARM_Disasm::DecodePackingSaturationReversal(u32 insn) {
|
||||
u32 op1 = BITS(insn, 20, 22);
|
||||
u32 a = BITS(insn, 16, 19);
|
||||
u32 op2 = BITS(insn, 5, 7);
|
||||
|
||||
switch (op1) {
|
||||
case 0x0:
|
||||
|
|
@ -1335,16 +1337,16 @@ Opcode ARM_Disasm::DecodePackingSaturationReversal(uint32_t insn) {
|
|||
return OP_UNDEFINED;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::DecodeMUL(uint32_t insn) {
|
||||
uint8_t bit24 = (insn >> 24) & 0x1;
|
||||
Opcode ARM_Disasm::DecodeMUL(u32 insn) {
|
||||
u8 bit24 = (insn >> 24) & 0x1;
|
||||
if (bit24 != 0) {
|
||||
// This is an unexpected bit pattern. Create an undefined
|
||||
// instruction in case this is ever executed.
|
||||
return OP_UNDEFINED;
|
||||
}
|
||||
uint8_t bit23 = (insn >> 23) & 0x1;
|
||||
uint8_t bit22_U = (insn >> 22) & 0x1;
|
||||
uint8_t bit21_A = (insn >> 21) & 0x1;
|
||||
u8 bit23 = (insn >> 23) & 0x1;
|
||||
u8 bit22_U = (insn >> 22) & 0x1;
|
||||
u8 bit21_A = (insn >> 21) & 0x1;
|
||||
if (bit23 == 0) {
|
||||
// 32-bit multiply
|
||||
if (bit22_U != 0) {
|
||||
|
|
@ -1369,10 +1371,10 @@ Opcode ARM_Disasm::DecodeMUL(uint32_t insn) {
|
|||
return OP_SMLAL;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::DecodeMSRImmAndHints(uint32_t insn) {
|
||||
uint32_t op = BIT(insn, 22);
|
||||
uint32_t op1 = BITS(insn, 16, 19);
|
||||
uint32_t op2 = BITS(insn, 0, 7);
|
||||
Opcode ARM_Disasm::DecodeMSRImmAndHints(u32 insn) {
|
||||
u32 op = BIT(insn, 22);
|
||||
u32 op1 = BITS(insn, 16, 19);
|
||||
u32 op2 = BITS(insn, 0, 7);
|
||||
|
||||
if (op == 0 && op1 == 0) {
|
||||
switch (op2) {
|
||||
|
|
@ -1394,10 +1396,10 @@ Opcode ARM_Disasm::DecodeMSRImmAndHints(uint32_t insn) {
|
|||
return OP_MSR;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::DecodeMediaMulDiv(uint32_t insn) {
|
||||
uint32_t op1 = BITS(insn, 20, 22);
|
||||
uint32_t op2_h = BITS(insn, 6, 7);
|
||||
uint32_t a = BITS(insn, 12, 15);
|
||||
Opcode ARM_Disasm::DecodeMediaMulDiv(u32 insn) {
|
||||
u32 op1 = BITS(insn, 20, 22);
|
||||
u32 op2_h = BITS(insn, 6, 7);
|
||||
u32 a = BITS(insn, 12, 15);
|
||||
|
||||
switch (op1) {
|
||||
case 0x0:
|
||||
|
|
@ -1436,10 +1438,10 @@ Opcode ARM_Disasm::DecodeMediaMulDiv(uint32_t insn) {
|
|||
return OP_UNDEFINED;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::DecodeMedia(uint32_t insn) {
|
||||
uint32_t op1 = BITS(insn, 20, 24);
|
||||
uint32_t rd = BITS(insn, 12, 15);
|
||||
uint32_t op2 = BITS(insn, 5, 7);
|
||||
Opcode ARM_Disasm::DecodeMedia(u32 insn) {
|
||||
u32 op1 = BITS(insn, 20, 24);
|
||||
u32 rd = BITS(insn, 12, 15);
|
||||
u32 op2 = BITS(insn, 5, 7);
|
||||
|
||||
switch (BITS(op1, 3, 4)) {
|
||||
case 0x0:
|
||||
|
|
@ -1464,9 +1466,9 @@ Opcode ARM_Disasm::DecodeMedia(uint32_t insn) {
|
|||
return OP_UNDEFINED;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::DecodeLDRH(uint32_t insn) {
|
||||
uint8_t is_load = (insn >> 20) & 0x1;
|
||||
uint8_t bits_65 = (insn >> 5) & 0x3;
|
||||
Opcode ARM_Disasm::DecodeLDRH(u32 insn) {
|
||||
u8 is_load = (insn >> 20) & 0x1;
|
||||
u8 bits_65 = (insn >> 5) & 0x3;
|
||||
if (is_load) {
|
||||
if (bits_65 == 0x1) {
|
||||
// Load unsigned halfword
|
||||
|
|
@ -1494,12 +1496,12 @@ Opcode ARM_Disasm::DecodeLDRH(uint32_t insn) {
|
|||
return OP_STRH;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::DecodeALU(uint32_t insn) {
|
||||
uint8_t is_immed = (insn >> 25) & 0x1;
|
||||
uint8_t opcode = (insn >> 21) & 0xf;
|
||||
uint8_t bit_s = (insn >> 20) & 1;
|
||||
uint8_t shift_is_reg = (insn >> 4) & 1;
|
||||
uint8_t bit7 = (insn >> 7) & 1;
|
||||
Opcode ARM_Disasm::DecodeALU(u32 insn) {
|
||||
u8 is_immed = (insn >> 25) & 0x1;
|
||||
u8 opcode = (insn >> 21) & 0xf;
|
||||
u8 bit_s = (insn >> 20) & 1;
|
||||
u8 shift_is_reg = (insn >> 4) & 1;
|
||||
u8 bit7 = (insn >> 7) & 1;
|
||||
if (!is_immed && shift_is_reg && (bit7 != 0)) {
|
||||
// This is an unexpected bit pattern. Create an undefined
|
||||
// instruction in case this is ever executed.
|
||||
|
|
|
|||
|
|
@ -2,9 +2,10 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
#include <cstdint>
|
||||
#include <string>
|
||||
|
||||
#include "common/common_types.h"
|
||||
|
||||
// Note: this list of opcodes must match the list used to initialize
|
||||
// the opflags[] array in opcode.cpp.
|
||||
enum Opcode {
|
||||
|
|
@ -191,48 +192,48 @@ enum Opcode {
|
|||
|
||||
class ARM_Disasm {
|
||||
public:
|
||||
static std::string Disassemble(uint32_t addr, uint32_t insn);
|
||||
static Opcode Decode(uint32_t insn);
|
||||
static std::string Disassemble(u32 addr, u32 insn);
|
||||
static Opcode Decode(u32 insn);
|
||||
|
||||
private:
|
||||
static Opcode Decode00(uint32_t insn);
|
||||
static Opcode Decode01(uint32_t insn);
|
||||
static Opcode Decode10(uint32_t insn);
|
||||
static Opcode Decode11(uint32_t insn);
|
||||
static Opcode DecodeSyncPrimitive(uint32_t insn);
|
||||
static Opcode DecodeParallelAddSub(uint32_t insn);
|
||||
static Opcode DecodePackingSaturationReversal(uint32_t insn);
|
||||
static Opcode DecodeMUL(uint32_t insn);
|
||||
static Opcode DecodeMSRImmAndHints(uint32_t insn);
|
||||
static Opcode DecodeMediaMulDiv(uint32_t insn);
|
||||
static Opcode DecodeMedia(uint32_t insn);
|
||||
static Opcode DecodeLDRH(uint32_t insn);
|
||||
static Opcode DecodeALU(uint32_t insn);
|
||||
static Opcode Decode00(u32 insn);
|
||||
static Opcode Decode01(u32 insn);
|
||||
static Opcode Decode10(u32 insn);
|
||||
static Opcode Decode11(u32 insn);
|
||||
static Opcode DecodeSyncPrimitive(u32 insn);
|
||||
static Opcode DecodeParallelAddSub(u32 insn);
|
||||
static Opcode DecodePackingSaturationReversal(u32 insn);
|
||||
static Opcode DecodeMUL(u32 insn);
|
||||
static Opcode DecodeMSRImmAndHints(u32 insn);
|
||||
static Opcode DecodeMediaMulDiv(u32 insn);
|
||||
static Opcode DecodeMedia(u32 insn);
|
||||
static Opcode DecodeLDRH(u32 insn);
|
||||
static Opcode DecodeALU(u32 insn);
|
||||
|
||||
static std::string DisassembleALU(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleBranch(uint32_t addr, Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleBX(uint32_t insn);
|
||||
static std::string DisassembleBKPT(uint32_t insn);
|
||||
static std::string DisassembleCLZ(uint32_t insn);
|
||||
static std::string DisassembleMediaMulDiv(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleMemblock(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleMem(uint32_t insn);
|
||||
static std::string DisassembleMemHalf(uint32_t insn);
|
||||
static std::string DisassembleMCR(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleMLA(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleUMLAL(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleMUL(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleMRS(uint32_t insn);
|
||||
static std::string DisassembleMSR(uint32_t insn);
|
||||
static std::string DisassembleNoOperands(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleParallelAddSub(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassemblePKH(uint32_t insn);
|
||||
static std::string DisassemblePLD(uint32_t insn);
|
||||
static std::string DisassembleREV(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleREX(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleSAT(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleSEL(uint32_t insn);
|
||||
static std::string DisassembleSWI(uint32_t insn);
|
||||
static std::string DisassembleSWP(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleXT(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleALU(Opcode opcode, u32 insn);
|
||||
static std::string DisassembleBranch(u32 addr, Opcode opcode, u32 insn);
|
||||
static std::string DisassembleBX(u32 insn);
|
||||
static std::string DisassembleBKPT(u32 insn);
|
||||
static std::string DisassembleCLZ(u32 insn);
|
||||
static std::string DisassembleMediaMulDiv(Opcode opcode, u32 insn);
|
||||
static std::string DisassembleMemblock(Opcode opcode, u32 insn);
|
||||
static std::string DisassembleMem(u32 insn);
|
||||
static std::string DisassembleMemHalf(u32 insn);
|
||||
static std::string DisassembleMCR(Opcode opcode, u32 insn);
|
||||
static std::string DisassembleMLA(Opcode opcode, u32 insn);
|
||||
static std::string DisassembleUMLAL(Opcode opcode, u32 insn);
|
||||
static std::string DisassembleMUL(Opcode opcode, u32 insn);
|
||||
static std::string DisassembleMRS(u32 insn);
|
||||
static std::string DisassembleMSR(u32 insn);
|
||||
static std::string DisassembleNoOperands(Opcode opcode, u32 insn);
|
||||
static std::string DisassembleParallelAddSub(Opcode opcode, u32 insn);
|
||||
static std::string DisassemblePKH(u32 insn);
|
||||
static std::string DisassemblePLD(u32 insn);
|
||||
static std::string DisassembleREV(Opcode opcode, u32 insn);
|
||||
static std::string DisassembleREX(Opcode opcode, u32 insn);
|
||||
static std::string DisassembleSAT(Opcode opcode, u32 insn);
|
||||
static std::string DisassembleSEL(u32 insn);
|
||||
static std::string DisassembleSWI(u32 insn);
|
||||
static std::string DisassembleSWP(Opcode opcode, u32 insn);
|
||||
static std::string DisassembleXT(Opcode opcode, u32 insn);
|
||||
};
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#include <algorithm>
|
||||
#include <cstdio>
|
||||
|
||||
#include "common/common_types.h"
|
||||
#include "common/logging/log.h"
|
||||
#include "common/profiler.h"
|
||||
|
||||
|
|
@ -759,8 +760,8 @@ struct bx_inst {
|
|||
|
||||
struct blx_inst {
|
||||
union {
|
||||
int32_t signed_immed_24;
|
||||
uint32_t Rm;
|
||||
s32 signed_immed_24;
|
||||
u32 Rm;
|
||||
} val;
|
||||
unsigned int inst;
|
||||
};
|
||||
|
|
@ -3544,7 +3545,7 @@ static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) {
|
|||
size++;
|
||||
// If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM instruction
|
||||
if (cpu->TFlag) {
|
||||
uint32_t arm_inst;
|
||||
u32 arm_inst;
|
||||
ThumbDecodeStatus state = DecodeThumbInstruction(inst, phys_addr, &arm_inst, &inst_size, &inst_base);
|
||||
|
||||
// We have translated the Thumb branch instruction in the Thumb decoder
|
||||
|
|
@ -4215,8 +4216,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
|
|||
CPS_INST:
|
||||
{
|
||||
cps_inst *inst_cream = (cps_inst *)inst_base->component;
|
||||
uint32_t aif_val = 0;
|
||||
uint32_t aif_mask = 0;
|
||||
u32 aif_val = 0;
|
||||
u32 aif_mask = 0;
|
||||
if (cpu->InAPrivilegedMode()) {
|
||||
if (inst_cream->imod1) {
|
||||
if (inst_cream->A) {
|
||||
|
|
@ -4710,11 +4711,11 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
|
|||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
mla_inst* inst_cream = (mla_inst*)inst_base->component;
|
||||
|
||||
uint64_t rm = RM;
|
||||
uint64_t rs = RS;
|
||||
uint64_t rn = RN;
|
||||
u64 rm = RM;
|
||||
u64 rs = RS;
|
||||
u64 rn = RN;
|
||||
|
||||
RD = static_cast<uint32_t>((rm * rs + rn) & 0xffffffff);
|
||||
RD = static_cast<u32>((rm * rs + rn) & 0xffffffff);
|
||||
if (inst_cream->S) {
|
||||
UPDATE_NFLAG(RD);
|
||||
UPDATE_ZFLAG(RD);
|
||||
|
|
@ -4819,7 +4820,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
|
|||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
msr_inst* inst_cream = (msr_inst*)inst_base->component;
|
||||
const uint32_t UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020;
|
||||
const u32 UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020;
|
||||
unsigned int inst = inst_cream->inst;
|
||||
unsigned int operand;
|
||||
|
||||
|
|
@ -4829,9 +4830,9 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
|
|||
} else {
|
||||
operand = cpu->Reg[BITS(inst, 0, 3)];
|
||||
}
|
||||
uint32_t byte_mask = (BIT(inst, 16) ? 0xff : 0) | (BIT(inst, 17) ? 0xff00 : 0)
|
||||
u32 byte_mask = (BIT(inst, 16) ? 0xff : 0) | (BIT(inst, 17) ? 0xff00 : 0)
|
||||
| (BIT(inst, 18) ? 0xff0000 : 0) | (BIT(inst, 19) ? 0xff000000 : 0);
|
||||
uint32_t mask = 0;
|
||||
u32 mask = 0;
|
||||
if (!inst_cream->R) {
|
||||
if (cpu->InAPrivilegedMode()) {
|
||||
if ((operand & StateMask) != 0) {
|
||||
|
|
@ -4864,9 +4865,9 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
|
|||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
mul_inst* inst_cream = (mul_inst*)inst_base->component;
|
||||
|
||||
uint64_t rm = RM;
|
||||
uint64_t rs = RS;
|
||||
RD = static_cast<uint32_t>((rm * rs) & 0xffffffff);
|
||||
u64 rm = RM;
|
||||
u64 rs = RS;
|
||||
RD = static_cast<u32>((rm * rs) & 0xffffffff);
|
||||
if (inst_cream->S) {
|
||||
UPDATE_NFLAG(RD);
|
||||
UPDATE_ZFLAG(RD);
|
||||
|
|
@ -5532,7 +5533,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
|
|||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
smla_inst* inst_cream = (smla_inst*)inst_base->component;
|
||||
int32_t operand1, operand2;
|
||||
s32 operand1, operand2;
|
||||
if (inst_cream->x == 0)
|
||||
operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15);
|
||||
else
|
||||
|
|
@ -5771,7 +5772,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
|
|||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
smul_inst* inst_cream = (smul_inst*)inst_base->component;
|
||||
uint32_t operand1, operand2;
|
||||
u32 operand1, operand2;
|
||||
if (inst_cream->x == 0)
|
||||
operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15);
|
||||
else
|
||||
|
|
@ -5792,15 +5793,15 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
|
|||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
umull_inst* inst_cream = (umull_inst*)inst_base->component;
|
||||
int64_t rm = RM;
|
||||
int64_t rs = RS;
|
||||
s64 rm = RM;
|
||||
s64 rs = RS;
|
||||
if (BIT(rm, 31)) {
|
||||
rm |= 0xffffffff00000000LL;
|
||||
}
|
||||
if (BIT(rs, 31)) {
|
||||
rs |= 0xffffffff00000000LL;
|
||||
}
|
||||
int64_t rst = rm * rs;
|
||||
s64 rst = rm * rs;
|
||||
RDHI = BITS(rst, 32, 63);
|
||||
RDLO = BITS(rst, 0, 31);
|
||||
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
/* Note: this file handles interface with arm core and vfp registers */
|
||||
|
||||
#include "common/common_funcs.h"
|
||||
#include "common/common_types.h"
|
||||
#include "common/logging/log.h"
|
||||
|
||||
#include "core/arm/skyeye_common/armstate.h"
|
||||
|
|
@ -110,30 +111,30 @@ void VMOVR(ARMul_State* state, u32 single, u32 d, u32 m)
|
|||
}
|
||||
|
||||
/* Miscellaneous functions */
|
||||
int32_t vfp_get_float(ARMul_State* state, unsigned int reg)
|
||||
s32 vfp_get_float(ARMul_State* state, unsigned int reg)
|
||||
{
|
||||
LOG_TRACE(Core_ARM11, "VFP get float: s%d=[%08x]\n", reg, state->ExtReg[reg]);
|
||||
return state->ExtReg[reg];
|
||||
}
|
||||
|
||||
void vfp_put_float(ARMul_State* state, int32_t val, unsigned int reg)
|
||||
void vfp_put_float(ARMul_State* state, s32 val, unsigned int reg)
|
||||
{
|
||||
LOG_TRACE(Core_ARM11, "VFP put float: s%d <= [%08x]\n", reg, val);
|
||||
state->ExtReg[reg] = val;
|
||||
}
|
||||
|
||||
uint64_t vfp_get_double(ARMul_State* state, unsigned int reg)
|
||||
u64 vfp_get_double(ARMul_State* state, unsigned int reg)
|
||||
{
|
||||
uint64_t result = ((uint64_t) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2];
|
||||
u64 result = ((u64) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2];
|
||||
LOG_TRACE(Core_ARM11, "VFP get double: s[%d-%d]=[%016llx]\n", reg * 2 + 1, reg * 2, result);
|
||||
return result;
|
||||
}
|
||||
|
||||
void vfp_put_double(ARMul_State* state, uint64_t val, unsigned int reg)
|
||||
void vfp_put_double(ARMul_State* state, u64 val, unsigned int reg)
|
||||
{
|
||||
LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg * 2 + 1, reg * 2, (uint32_t)(val >> 32), (uint32_t)(val & 0xffffffff));
|
||||
state->ExtReg[reg*2] = (uint32_t) (val & 0xffffffff);
|
||||
state->ExtReg[reg*2+1] = (uint32_t) (val>>32);
|
||||
LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg * 2 + 1, reg * 2, (u32)(val >> 32), (u32)(val & 0xffffffff));
|
||||
state->ExtReg[reg*2] = (u32) (val & 0xffffffff);
|
||||
state->ExtReg[reg*2+1] = (u32) (val>>32);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
#include <cstdint>
|
||||
#include "common/common_types.h"
|
||||
|
||||
namespace CiTrace {
|
||||
|
||||
|
|
@ -17,38 +17,38 @@ struct CTHeader {
|
|||
return "CiTr";
|
||||
}
|
||||
|
||||
static uint32_t ExpectedVersion() {
|
||||
static u32 ExpectedVersion() {
|
||||
return 1;
|
||||
}
|
||||
|
||||
char magic[4];
|
||||
uint32_t version;
|
||||
uint32_t header_size;
|
||||
u32 version;
|
||||
u32 header_size;
|
||||
|
||||
struct {
|
||||
// NOTE: Register range sizes are technically hardware-constants, but the actual limits
|
||||
// aren't known. Hence we store the presumed limits along the offsets.
|
||||
// Sizes are given in uint32_t units.
|
||||
uint32_t gpu_registers;
|
||||
uint32_t gpu_registers_size;
|
||||
uint32_t lcd_registers;
|
||||
uint32_t lcd_registers_size;
|
||||
uint32_t pica_registers;
|
||||
uint32_t pica_registers_size;
|
||||
uint32_t default_attributes;
|
||||
uint32_t default_attributes_size;
|
||||
uint32_t vs_program_binary;
|
||||
uint32_t vs_program_binary_size;
|
||||
uint32_t vs_swizzle_data;
|
||||
uint32_t vs_swizzle_data_size;
|
||||
uint32_t vs_float_uniforms;
|
||||
uint32_t vs_float_uniforms_size;
|
||||
uint32_t gs_program_binary;
|
||||
uint32_t gs_program_binary_size;
|
||||
uint32_t gs_swizzle_data;
|
||||
uint32_t gs_swizzle_data_size;
|
||||
uint32_t gs_float_uniforms;
|
||||
uint32_t gs_float_uniforms_size;
|
||||
// Sizes are given in u32 units.
|
||||
u32 gpu_registers;
|
||||
u32 gpu_registers_size;
|
||||
u32 lcd_registers;
|
||||
u32 lcd_registers_size;
|
||||
u32 pica_registers;
|
||||
u32 pica_registers_size;
|
||||
u32 default_attributes;
|
||||
u32 default_attributes_size;
|
||||
u32 vs_program_binary;
|
||||
u32 vs_program_binary_size;
|
||||
u32 vs_swizzle_data;
|
||||
u32 vs_swizzle_data_size;
|
||||
u32 vs_float_uniforms;
|
||||
u32 vs_float_uniforms_size;
|
||||
u32 gs_program_binary;
|
||||
u32 gs_program_binary_size;
|
||||
u32 gs_swizzle_data;
|
||||
u32 gs_swizzle_data_size;
|
||||
u32 gs_float_uniforms;
|
||||
u32 gs_float_uniforms_size;
|
||||
|
||||
// Other things we might want to store here:
|
||||
// - Initial framebuffer data, maybe even a full copy of FCRAM/VRAM
|
||||
|
|
@ -56,27 +56,27 @@ struct CTHeader {
|
|||
// - Lookup tables for procedural textures
|
||||
} initial_state_offsets;
|
||||
|
||||
uint32_t stream_offset;
|
||||
uint32_t stream_size;
|
||||
u32 stream_offset;
|
||||
u32 stream_size;
|
||||
};
|
||||
|
||||
enum CTStreamElementType : uint32_t {
|
||||
enum CTStreamElementType : u32 {
|
||||
FrameMarker = 0xE1,
|
||||
MemoryLoad = 0xE2,
|
||||
RegisterWrite = 0xE3,
|
||||
};
|
||||
|
||||
struct CTMemoryLoad {
|
||||
uint32_t file_offset;
|
||||
uint32_t size;
|
||||
uint32_t physical_address;
|
||||
uint32_t pad;
|
||||
u32 file_offset;
|
||||
u32 size;
|
||||
u32 physical_address;
|
||||
u32 pad;
|
||||
};
|
||||
|
||||
struct CTRegisterWrite {
|
||||
uint32_t physical_address;
|
||||
u32 physical_address;
|
||||
|
||||
enum : uint32_t {
|
||||
enum : u32 {
|
||||
SIZE_8 = 0xD1,
|
||||
SIZE_16 = 0xD2,
|
||||
SIZE_32 = 0xD3,
|
||||
|
|
@ -84,7 +84,7 @@ struct CTRegisterWrite {
|
|||
} size;
|
||||
|
||||
// TODO: Make it clearer which bits of this member are used for sizes other than 32 bits
|
||||
uint64_t value;
|
||||
u64 value;
|
||||
};
|
||||
|
||||
struct CTStreamElement {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue