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armemu: Implement SMMUL, SMMLA, and SMMLS.

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This commit is contained in:
Lioncash 2014-12-25 13:33:49 -05:00
parent 2bbbe68399
commit 35dbfc7ab0
1 changed files with 30 additions and 2 deletions
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32
src/core/arm/interpreter/armemu.cpp
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@ -6506,8 +6506,36 @@ L_stm_s_takeabort:
case 0x74: case 0x74:
printf ("Unhandled v6 insn: smlald/smlsld\n"); printf ("Unhandled v6 insn: smlald/smlsld\n");
break; break;
case 0x75: case 0x75: // SMMLA, SMMUL, and SMMLS
printf ("Unhandled v6 insn: smmla/smmls/smmul\n"); {
const u8 rm_idx = BITS(8, 11);
const u8 rn_idx = BITS(0, 3);
const u8 ra_idx = BITS(12, 15);
const u8 rd_idx = BITS(16, 19);
const bool do_round = (BIT(5) == 1);
const u32 rm_val = state->Reg[rm_idx];
const u32 rn_val = state->Reg[rn_idx];
// Assume SMMUL by default.
s64 result = (s64)(s32)rn_val * (s64)(s32)rm_val;
if (ra_idx != 15) {
const u32 ra_val = state->Reg[ra_idx];
// SMMLA, otherwise SMMLS
if (BIT(6) == 0)
result += ((s64)ra_val << 32);
else
result = ((s64)ra_val << 32) - result;
}
if (do_round)
result += 0x80000000;
state->Reg[rd_idx] = ((result >> 32) & 0xFFFFFFFF);
return 1;
}
break; break;
case 0x78: case 0x78:
if (BITS(20, 24) == 0x18) if (BITS(20, 24) == 0x18)