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https://github.com/PabloMK7/citra.git
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Update teakra to fix macos issue; address comment feedbacks
This commit is contained in:
Weiyi Wang
parent
e3ac248487
commit
05c372bf6c
7 changed files with 65 additions and 44 deletions
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@ -3,6 +3,7 @@
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// Refer to the license.txt file included.
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#include <array>
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#include <teakra/teakra.h>
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#include "audio_core/lle/lle.h"
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#include "common/assert.h"
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#include "common/bit_field.h"
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@ -10,7 +11,6 @@
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#include "core/core.h"
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#include "core/core_timing.h"
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#include "core/hle/service/dsp/dsp_dsp.h"
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#include "teakra/teakra.h"
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namespace AudioCore {
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@ -22,11 +22,11 @@ enum class SegmentType : u8 {
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class Dsp1 {
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public:
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Dsp1(const std::vector<u8>& raw);
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explicit Dsp1(const std::vector<u8>& raw);
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struct Header {
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std::array<u8, 0x100> signature;
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std::array<u8, 4> magic;
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std::array<u8, 0x4> magic;
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u32_le binary_size;
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u16_le memory_layout;
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INSERT_PADDING_BYTES(3);
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@ -72,7 +72,7 @@ Dsp1::Dsp1(const std::vector<u8>& raw) {
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raw.begin() + header.segments[i].offset + header.segments[i].size);
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segment.memory_type = header.segments[i].memory_type;
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segment.target = header.segments[i].address;
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segments.push_back(segment);
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segments.push_back(std::move(segment));
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}
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}
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@ -83,6 +83,26 @@ struct PipeStatus {
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u16_le write_bptr;
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u8 slot_index;
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u8 flags;
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static constexpr u16 WrapBit = 0x8000;
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static constexpr u16 PtrMask = 0x7FFF;
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bool IsFull() const {
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return (read_bptr ^ write_bptr) == WrapBit;
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}
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bool IsEmpty() const {
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return (read_bptr ^ write_bptr) == 0;
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}
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/*
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* IsWrapped: Are read and write pointers not in the same pass.
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* false: ----[xxxx]----
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* true: xxxx]----[xxxx (data is wrapping around the end)
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*/
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bool IsWrapped() const {
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return (read_bptr ^ write_bptr) >= WrapBit;
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}
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};
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static_assert(sizeof(PipeStatus) == 10);
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@ -93,7 +113,7 @@ enum class PipeDirection : u8 {
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};
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static u8 PipeIndexToSlotIndex(u8 pipe_index, PipeDirection direction) {
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return (pipe_index << 1) + (u8)direction;
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return (pipe_index << 1) + static_cast<u8>(direction);
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}
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struct DspLle::Impl final {
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@ -111,7 +131,9 @@ struct DspLle::Impl final {
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Core::TimingEventType* teakra_slice_event;
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bool loaded = false;
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static constexpr unsigned TeakraSlice = 20000;
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static constexpr u32 DspDataOffset = 0x40000;
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static constexpr u32 TeakraSlice = 20000;
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void RunTeakraSlice() {
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teakra.Run(TeakraSlice);
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}
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@ -128,7 +150,7 @@ struct DspLle::Impl final {
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u8* GetDspDataPointer(u32 baddr) {
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auto& memory = teakra.GetDspMemory();
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return &memory[0x40000 + baddr];
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return &memory[DspDataOffset + baddr];
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}
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PipeStatus GetPipeStatus(u8 pipe_index, PipeDirection direction) {
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@ -156,16 +178,15 @@ struct DspLle::Impl final {
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PipeStatus pipe_status = GetPipeStatus(pipe_index, PipeDirection::CPUtoDSP);
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bool need_update = false;
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const u8* buffer_ptr = data.data();
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u16 bsize = (u16)data.size();
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u16 bsize = static_cast<u16>(data.size());
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while (bsize != 0) {
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u16 x = pipe_status.read_bptr ^ pipe_status.write_bptr;
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ASSERT_MSG(x != 0x8000, "Pipe is Full");
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ASSERT_MSG(!pipe_status.IsFull(), "Pipe is Full");
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u16 write_bend;
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if (x > 0x8000)
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write_bend = pipe_status.read_bptr & 0x7FFF;
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if (pipe_status.IsWrapped())
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write_bend = pipe_status.read_bptr & PipeStatus::PtrMask;
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else
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write_bend = pipe_status.bsize;
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u16 write_bbegin = pipe_status.write_bptr & 0x7FFF;
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u16 write_bbegin = pipe_status.write_bptr & PipeStatus::PtrMask;
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ASSERT_MSG(write_bend > write_bbegin,
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"Pipe is in inconsistent state: end {:04X} <= begin {:04X}, size {:04X}",
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write_bend, write_bbegin, pipe_status.bsize);
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@ -175,11 +196,11 @@ struct DspLle::Impl final {
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buffer_ptr += write_bsize;
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pipe_status.write_bptr += write_bsize;
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bsize -= write_bsize;
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ASSERT_MSG((pipe_status.write_bptr & 0x7FFF) <= pipe_status.bsize,
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ASSERT_MSG((pipe_status.write_bptr & PipeStatus::PtrMask) <= pipe_status.bsize,
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"Pipe is in inconsistent state: write > size");
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if ((pipe_status.write_bptr & 0x7FFF) == pipe_status.bsize) {
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pipe_status.write_bptr &= 0x8000;
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pipe_status.write_bptr ^= 0x8000;
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if ((pipe_status.write_bptr & PipeStatus::PtrMask) == pipe_status.bsize) {
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pipe_status.write_bptr &= PipeStatus::WrapBit;
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pipe_status.write_bptr ^= PipeStatus::WrapBit;
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}
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need_update = true;
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}
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@ -197,15 +218,14 @@ struct DspLle::Impl final {
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std::vector<u8> data(bsize);
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u8* buffer_ptr = data.data();
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while (bsize != 0) {
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u16 x = pipe_status.read_bptr ^ pipe_status.write_bptr;
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ASSERT_MSG(x != 0, "Pipe is empty");
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ASSERT_MSG(!pipe_status.IsEmpty(), "Pipe is empty");
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u16 read_bend;
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if (x >= 0x8000) {
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if (pipe_status.IsWrapped()) {
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read_bend = pipe_status.bsize;
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} else {
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read_bend = pipe_status.write_bptr & 0x7FFF;
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read_bend = pipe_status.write_bptr & PipeStatus::PtrMask;
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}
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u16 read_bbegin = pipe_status.read_bptr & 0x7FFF;
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u16 read_bbegin = pipe_status.read_bptr & PipeStatus::PtrMask;
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ASSERT(read_bend > read_bbegin);
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u16 read_bsize = std::min<u16>(bsize, read_bend - read_bbegin);
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std::memcpy(buffer_ptr, GetDspDataPointer(pipe_status.waddress * 2 + read_bbegin),
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@ -213,11 +233,11 @@ struct DspLle::Impl final {
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buffer_ptr += read_bsize;
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pipe_status.read_bptr += read_bsize;
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bsize -= read_bsize;
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ASSERT_MSG((pipe_status.read_bptr & 0x7FFF) <= pipe_status.bsize,
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ASSERT_MSG((pipe_status.read_bptr & PipeStatus::PtrMask) <= pipe_status.bsize,
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"Pipe is in inconsistent state: read > size");
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if ((pipe_status.read_bptr & 0x7FFF) == pipe_status.bsize) {
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pipe_status.read_bptr &= 0x8000;
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pipe_status.read_bptr ^= 0x8000;
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if ((pipe_status.read_bptr & PipeStatus::PtrMask) == pipe_status.bsize) {
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pipe_status.read_bptr &= PipeStatus::WrapBit;
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pipe_status.read_bptr ^= PipeStatus::WrapBit;
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}
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need_update = true;
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}
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@ -232,10 +252,10 @@ struct DspLle::Impl final {
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u16 GetPipeReadableSize(u8 pipe_index) {
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PipeStatus pipe_status = GetPipeStatus(pipe_index, PipeDirection::DSPtoCPU);
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u16 size = pipe_status.write_bptr - pipe_status.read_bptr;
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if ((pipe_status.read_bptr ^ pipe_status.write_bptr) >= 0x8000) {
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if (pipe_status.IsWrapped()) {
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size += pipe_status.bsize;
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}
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return size & 0x7FFF;
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return size & PipeStatus::PtrMask;
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}
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void LoadComponent(const std::vector<u8>& buffer) {
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@ -249,7 +269,7 @@ struct DspLle::Impl final {
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Dsp1 dsp(buffer);
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auto& dsp_memory = teakra.GetDspMemory();
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u8* program = dsp_memory.data();
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u8* data = dsp_memory.data() + 0x40000;
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u8* data = dsp_memory.data() + DspDataOffset;
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for (const auto& segment : dsp.segments) {
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if (segment.memory_type == SegmentType::ProgramA ||
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segment.memory_type == SegmentType::ProgramB) {
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@ -265,10 +285,11 @@ struct DspLle::Impl final {
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// Wait for initialization
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if (dsp.recv_data_on_start) {
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for (unsigned i = 0; i < 3; ++i) {
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while (!teakra.RecvDataIsReady(i))
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RunTeakraSlice();
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ASSERT(teakra.RecvData(i) == 1);
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for (u8 i = 0; i < 3; ++i) {
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do {
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while (!teakra.RecvDataIsReady(i))
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RunTeakraSlice();
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} while (teakra.RecvData(i) != 1);
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}
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}
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@ -287,10 +308,11 @@ struct DspLle::Impl final {
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}
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// Send finalization signal
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constexpr u16 FinalizeSignal = 0x8000;
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while (!teakra.SendDataIsEmpty(2))
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RunTeakraSlice();
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teakra.SendData(2, 0x8000);
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teakra.SendData(2, FinalizeSignal);
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// Wait for completion
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while (!teakra.RecvDataIsReady(2))
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@ -11,7 +11,7 @@ namespace AudioCore {
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class DspLle final : public DspInterface {
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public:
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explicit DspLle(Memory::MemorySystem& memory);
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~DspLle();
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~DspLle() override;
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u16 RecvData(u32 register_number) override;
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bool RecvDataIsReady(u32 register_number) const override;
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@ -29,7 +29,6 @@ public:
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private:
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struct Impl;
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friend struct Impl;
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std::unique_ptr<Impl> impl;
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};
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